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16 条记录 (耗时 0.034 秒)

    Enhanced selectivity for epitaxial deposition
    7.
    发明授权
    Enhanced selectivity for epitaxial deposition 有权
    增强外延沉积的选择性

    公开(公告)号：US06998305B2

    公开(公告)日：2006-02-14

    申请号：US10763948

    申请日：2004-01-23

    申请人： Chantal J. Arena ,  Joe P. Italiano ,  Paul D. Brabant

    发明人： Chantal J. Arena ,  Joe P. Italiano ,  Paul D. Brabant

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/66628 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/7834

    摘要： A method of forming an electronic component having elevated active areas is disclosed. The method comprises providing a semiconductor substrate in a processing chamber. The semiconductor substrate has disposed thereon a polycrystalline silicon gate and exposed active areas. The method further comprises performing a deposition process in which a silicon-source gas is supplied into the processing chamber to cause polycrystalline growth on the gate and epitaxial deposition on the active areas. The method further comprises performing a flash etch back process in which polycrystalline material is etched from the gate at a first etching rate and the epitaxial layer is etched from the active areas at a second etching rate. The first etching rate is faster than the second etching rate. The deposition process and the flash etch back process can be repeated cyclically, if desired. In certain other embodiments, the deposition process is a selective epitaxial deposition process, wherein growth occurs in non-oxide regions, but not in oxide regions.

    摘要翻译： 公开了一种形成具有升高的有效面积的电子部件的方法。 该方法包括在处理室中设置半导体衬底。 半导体衬底上设置有多晶硅栅极和暴露的有源区。 该方法还包括执行沉积工艺，其中将硅源气体供应到处理室中以在栅极上引起多晶生长并在有源区上进行外延沉积。 该方法还包括执行闪光回蚀工艺，其中以第一蚀刻速率从栅极蚀刻多晶材料，并且以第二蚀刻速率从有源区蚀刻外延层。 第一蚀刻速率比第二蚀刻速率快。 如果需要，沉积过程和闪光回蚀工艺可循环重复。 在某些其他实施例中，沉积工艺是选择性外延沉积工艺，其中生长发生在非氧化物区域中，但不在氧化物区域中发生。

    Low temperature load and bake
    8.
    发明授权
    Low temperature load and bake 有权
    低温负荷和烘烤

    公开(公告)号：US07462239B2

    公开(公告)日：2008-12-09

    申请号：US11433535

    申请日：2006-05-12

    申请人： Paul D. Brabant ,  Joe P. Italiano ,  Jianqing Wen

    发明人： Paul D. Brabant ,  Joe P. Italiano ,  Jianqing Wen

    IPC分类号： C30B25/10

    CPC分类号： C23C16/4408 ,  C23C16/0209 ,  C23C16/0227 ,  C23C16/4405 ,  C30B25/02 ,  C30B25/18 ,  C30B29/30 ,  C30B31/00 ,  H01L21/02046 ,  H01L21/02052 ,  Y10T117/10 ,  Y10T117/1004 ,  Y10T117/1008

    摘要： Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.

    摘要翻译： 提供了用于低温，快速烘烤以在原位沉积之前从半导体表面去除杂质的方法。 有利地，短的低温工艺消耗很少的热预算，使得该工艺适用于具有浅结的先进的高密度电路。 此外，通过低温烘烤，特别是结合烘烤前的低温等离子体清洗和低温晶片负载以及在低于常规外延沉积的温度下烘烤后沉积，可以大大提高产量。 该方法能够在半导体表面上外延沉积含硅层，特别是能够在硅锗基底层上进行外延沉积。 通过使用低温烘烤，可以清洁硅锗基底层以促进进一步的外延沉积，而不会松弛硅锗的应变晶体结构。

    Low temperature selective epitaxy of silicon germanium alloys employing cyclic deposit and etch
    10.
    发明授权
    Low temperature selective epitaxy of silicon germanium alloys employing cyclic deposit and etch 有权
    采用循环沉积和蚀刻的硅锗合金的低温选择性外延

    公开(公告)号：US08642454B2

    公开(公告)日：2014-02-04

    申请号：US13475503

    申请日：2012-05-18

    申请人： Paul D. Brabant ,  Keith Chung ,  Hong He ,  Devendra K. Sadana ,  Manabu Shinriki

    发明人： Paul D. Brabant ,  Keith Chung ,  Hong He ,  Devendra K. Sadana ,  Manabu Shinriki

    IPC分类号： H01L21/36 ,  H01L21/20

    CPC分类号： H01L21/0262 ,  C23C16/30 ,  C23C16/45523 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02636

    摘要： Cyclic deposit and etch (CDE) selective epitaxial growth employs an etch chemistry employing a combination of hydrogen chloride and a germanium-containing gas to provide selective deposition of a silicon germanium alloy at temperatures lower than 625° C. High strain epitaxial silicon germanium alloys having a germanium concentration greater than 35 atomic percent in a temperature range between 400° C. and 550° C. A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium-containing precursor gas is employed to deposit the silicon germanium alloy with thickness uniformity and at a high deposition rate during each deposition step in this temperature range. Presence of the germanium-containing gas in the etch chemistry enhances the etch rate of the deposited silicon germanium alloy material during the etch step.

    摘要翻译： 循环沉积和蚀刻（CDE）选择性外延生长采用采用氯化氢和含锗气体的组合的蚀刻化学法，以在低于625℃的温度下提供硅锗合金的选择性沉积。具有 在400℃和550℃之间的温度范围内的锗浓度大于35原子％。具有式SinH2n + 2的高阶硅烷，其中n是大于3的整数，与锗 - 在该温度范围内的每个沉积步骤中，使用含有前体气体来沉积具有厚度均匀性和高沉积速率的硅锗合金。 蚀刻化学中含锗气体的存在增强了在蚀刻步骤期间沉积的硅锗合金材料的蚀刻速率。