利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

371 条记录 (耗时 0.045 秒)

    Low temperature selective epitaxy of silicon germanium alloys employing cyclic deposit and etch
    1.
    发明授权
    Low temperature selective epitaxy of silicon germanium alloys employing cyclic deposit and etch 有权
    采用循环沉积和蚀刻的硅锗合金的低温选择性外延

    公开(公告)号：US08642454B2

    公开(公告)日：2014-02-04

    申请号：US13475503

    申请日：2012-05-18

    申请人： Paul D. Brabant ,  Keith Chung ,  Hong He ,  Devendra K. Sadana ,  Manabu Shinriki

    发明人： Paul D. Brabant ,  Keith Chung ,  Hong He ,  Devendra K. Sadana ,  Manabu Shinriki

    IPC分类号： H01L21/36 ,  H01L21/20

    CPC分类号： H01L21/0262 ,  C23C16/30 ,  C23C16/45523 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02636

    摘要： Cyclic deposit and etch (CDE) selective epitaxial growth employs an etch chemistry employing a combination of hydrogen chloride and a germanium-containing gas to provide selective deposition of a silicon germanium alloy at temperatures lower than 625° C. High strain epitaxial silicon germanium alloys having a germanium concentration greater than 35 atomic percent in a temperature range between 400° C. and 550° C. A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium-containing precursor gas is employed to deposit the silicon germanium alloy with thickness uniformity and at a high deposition rate during each deposition step in this temperature range. Presence of the germanium-containing gas in the etch chemistry enhances the etch rate of the deposited silicon germanium alloy material during the etch step.

    摘要翻译： 循环沉积和蚀刻（CDE）选择性外延生长采用采用氯化氢和含锗气体的组合的蚀刻化学法，以在低于625℃的温度下提供硅锗合金的选择性沉积。具有 在400℃和550℃之间的温度范围内的锗浓度大于35原子％。具有式SinH2n + 2的高阶硅烷，其中n是大于3的整数，与锗 - 在该温度范围内的每个沉积步骤中，使用含有前体气体来沉积具有厚度均匀性和高沉积速率的硅锗合金。 蚀刻化学中含锗气体的存在增强了在蚀刻步骤期间沉积的硅锗合金材料的蚀刻速率。

    EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2
    2.
    发明申请
    EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2 审中-公开
    首先使用HCl / GeH4 / H2SiCl2表面清洁的外延工艺

    公开(公告)号：US20130040438A1

    公开(公告)日：2013-02-14

    申请号：US13206248

    申请日：2011-08-09

    申请人： Thomas N. Adam ,  Hong He ,  Alexander Reznicek ,  Devendra K. Sadana ,  Paul D. Brabant ,  Keith Chung ,  Manabu Shinriki

    发明人： Thomas N. Adam ,  Hong He ,  Alexander Reznicek ,  Devendra K. Sadana ,  Paul D. Brabant ,  Keith Chung ,  Manabu Shinriki

    IPC分类号： H01L21/205 ,  H01L21/322

    CPC分类号： H01L21/0237 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02661

    摘要： A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.

    摘要翻译： 一种沉积外延层的方法，包括化学清洗半导体衬底的沉积表面，并在预烘烤温度下用含氢气体处理半导体衬底的沉积表面。 含氢气体处理可以在外延沉积室中进行。 含氢气体从半导体衬底的沉积表面去除含氧材料。 然后可以用包含至少一种盐酸（HCl），锗烷（GeH4）和二氯硅烷（H 2 SiCl 2））的气流来处理半导体衬底的沉积表面，该气流随着温度从 预烘烤温度达到外延沉积温度。 可以将至少一种源气体施加到沉积表面，用于材料层的外延沉积。

    LOW TEMPERATURE SELECTIVE EPITAXY OF SILICON GERMANIUM ALLOYS EMPLOYING CYCLIC DEPOSIT AND ETCH
    4.
    发明申请
    LOW TEMPERATURE SELECTIVE EPITAXY OF SILICON GERMANIUM ALLOYS EMPLOYING CYCLIC DEPOSIT AND ETCH 有权
    使用循环沉积和蚀刻的硅锗合金的低温选择性外延

    公开(公告)号：US20120295421A1

    公开(公告)日：2012-11-22

    申请号：US13475503

    申请日：2012-05-18

    申请人： Paul D. Brabant ,  Keith Chung ,  Hong He ,  Devendra K. Sadana ,  Manabu Shinriki

    发明人： Paul D. Brabant ,  Keith Chung ,  Hong He ,  Devendra K. Sadana ,  Manabu Shinriki

    IPC分类号： H01L21/20

    CPC分类号： H01L21/0262 ,  C23C16/30 ,  C23C16/45523 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02636

    摘要： Cyclic deposit and etch (CDE) selective epitaxial growth employs an etch chemistry employing a combination of hydrogen chloride and a germanium-containing gas to provide selective deposition of a silicon germanium alloy at temperatures lower than 625° C. High strain epitaxial silicon germanium alloys having a germanium concentration greater than 35 atomic percent in a temperature range between 400° C. and 550° C. A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium-containing precursor gas is employed to deposit the silicon germanium alloy with thickness uniformity and at a high deposition rate during each deposition step in this temperature range. Presence of the germanium-containing gas in the etch chemistry enhances the etch rate of the deposited silicon germanium alloy material during the etch step.

    摘要翻译： 循环沉积和蚀刻（CDE）选择性外延生长采用采用氯化氢和含锗气体的组合的蚀刻化学法，以在低于625℃的温度下提供硅锗合金的选择性沉积。具有 在400℃和550℃之间的温度范围内的锗浓度大于35原子％。具有式SinH2n + 2的高阶硅烷，其中n是大于3的整数，与锗 - 在该温度范围内的每个沉积步骤中，使用含有前体气体来沉积具有厚度均匀性和高沉积速率的硅锗合金。 蚀刻化学中含锗气体的存在增强了在蚀刻步骤期间沉积的硅锗合金材料的蚀刻速率。

    Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides
    9.
    发明授权
    Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides 有权
    具有超薄SOI层和掩埋氧化物的绝缘体上半导体（SOI）衬底

    公开(公告)号：US09059245B2

    公开(公告)日：2015-06-16

    申请号：US13483781

    申请日：2012-05-30

    申请人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76243

    摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.

    摘要翻译： 提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。 使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。 氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。 在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

    Method for controlled removal of a semiconductor device layer from a base substrate
    10.
    发明授权
    Method for controlled removal of a semiconductor device layer from a base substrate 有权
    从基底基板控制去除半导体器件层的方法

    公开(公告)号：US09059073B2

    公开(公告)日：2015-06-16

    申请号：US13603944

    申请日：2012-09-05

    申请人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Norma E. Sosa Cortes

    发明人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Norma E. Sosa Cortes

    IPC分类号： H01L21/20 ,  H01L21/18 ,  H01L21/78 ,  H01L21/02 ,  H01L31/18

    CPC分类号： H01L21/187 ,  H01L21/02002 ,  H01L21/7813 ,  H01L31/1892 ,  Y02E10/50

    摘要： A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.

    摘要翻译： 提供从基底基板去除半导体器件层的方法，其包括在基底基板的上表面上提供裂纹扩展层。 在裂纹扩展层上形成包括至少一个半导体器件的半导体器件层。 接下来，蚀刻裂纹扩展层的端部以在裂纹扩展层中引发裂纹。 蚀刻的裂纹扩展层然后被切割，以向半导体器件层的表面和另一个裂开的裂纹扩展层部分提供切割的裂纹扩展层部分到基底衬底的上表面。 从半导体器件层的表面去除切割的裂纹扩展层部分，并从基底基板的上表面除去另一个裂开的裂纹扩展层部分。