摘要:
The present invention provides a method and apparatus for increased efficiency for translation lookaside buffers by collapsing redundant translation table entries into a single translation table entry (TTE). In the present invention, each thread of a multithreaded processor is provided with multiple context registers. Each of these context registers is compared independently to the context of the TTE. If any of the contexts match (and the other match conditions are satisfied), then the translation is allowed to proceed. Two applications attempting to share one page but that still keep separate pages can then employ three total contexts. One context is for one application's private use; one of the contexts is for the other application's private use; and a third context is for the shared page. In one embodiment of the invention, two contexts are implemented per thread. However, the teachings of the present invention can be extended to a higher number of contexts per thread.
摘要:
A method is described that involves performing a checksum calculation on a section of data within an inbound packet before the section of data is first stored into a system memory. Another method is described that involves moving a section of data within an outbound packet from a system memory to an offload memory. Then, removing the section of data from the offload memory; and performing a checksum calculation on the section of data. An apparatus is described that includes a central processing unit that is communicatively coupled with a network processing offload unit, wherein the network processing offload unit calculates a checksum upon a section of data located within an inbound packet, and calculates a checksum upon a section of data within an outbound packet.
摘要:
In one embodiment, a processor comprises a plurality of processor cores and an interconnect to which the plurality of processor cores are coupled. Each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB). A first processor core is configured to broadcast a demap command on the interconnect responsive to executing a demap operation. The demap command identifies one or more translations to be invalidated in the TLBs, and remaining processor cores are configured to invalidate the translations in the respective TLBs. The remaining processor cores transmit a response to the first processor core, and the first processor core is configured to delay continued processing subsequent to the demap operation until the responses are received from each of the remaining processor cores.
摘要:
A non-impact keyless chuck suitable for use with manual or powered drivers is disclosed. The chuck comprises a body which carries a rotatable split nut having a relatively fine thread and a plurality of slidable jaws, which may be identical, driven by the rotatable nut. An anti-friction bearing is disposed between the rotatable nut and a bearing thrust ring mounted on the body. A clutch or torque limiting mechanism is provided to limit the tightening torque to a predetermined value while the loosening torque may be limited or unlimited. The front sleeve, and rear sleeve, if used, may be formed from a structural plastic to reduce manufacturing costs. A relatively soft elastomeric grip boot may be placed on the front sleeve to improve the grip and temporarily restrain and center the tool during chuck tightening or loosening operations. A relatively soft elastomeric grip boot may also be placed on the rear sleeve, if used.
摘要:
Methods and systems for processing data communicated over a network. In one aspect, an exemplary embodiment includes processing a first group of network packets in a first processor which executes a first network protocol stack, where the first group of network packets are communicated through a first network interface port, and processing a second group of network packets in a second processor which executes a second network protocol stack, where the second group of network packets is communicated through the first network interface port. Other methods and systems are also described.
摘要:
In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one update to the TLB is pending for at least one of a plurality of strands. Each strand comprises hardware to support a different thread of a plurality of concurrently activateable threads in the processor. The strands share the TLB, and the control unit is configured to delay a demap operation issued from one of the estrands responsive to the pending update, if any.
摘要:
A method and mechanism for controlling threads in a multithreaded multicore processor. A processor includes multiple cores, each of which are capable of executing multiple threads. A control register which is shared by each of the cores is utilized to control the status of the threads in the processing system. In one embodiment, the shared register includes a single bit for each thread in the processor. Depending upon the value written to a bit of the shared register, one of three results may occur with respect to a thread which corresponds to the bit. In one embodiment, writing a “0” to a bit of the shared register will cause a corresponding thread to be Parked. Writing a “1” to a bit of the shared register will cause a corresponding thread to either be UnParked or be Reset. Whether writing a “1” to a bit of the register causes the corresponding thread to be UnParked or Reset depends upon a state of the processor.
摘要:
A system and method for precisely identifying an instruction causing a performance-related event is disclosed. The instruction may be detected while in a pipeline stage of a microprocessor preceding a writeback stage and the microprocessor's architectural state may not be updated until after information identifying the instruction is captured. The instruction may be flushed from the pipeline, along with other instructions from the same thread. A hardware trap may be taken when the instruction is detected and/or when an event counter overflows or is within a given range of overflowing. A software trap handler may capture and/or log information identifying the instruction, such as one or more extended address elements, before returning control and initiating a retry of the instruction. The captured and/or logged information may be stored in an event space database usable by a data space profiler to identify performance bottlenecks in the application containing the instruction.
摘要:
A portable device, such as a pager-type device or card module, generates and guides a user through a customized smoking cessation plan. The device calculates intervals between smoking events (when the user is allowed to smoke) based on user input information and the day in the plan. The intervals increase as the plan progresses. The device alerts the user when a smoking event occurs. The user may place the device in a silent mode during periods when smoking would be inconvenient.
摘要:
A high-rise building comprises an exterior wall and a sheath, which is spaced in front of said wall. Vertically extending flow channels are provided between said wall and said sheath and are open at their bottom and top and may be used to supply air to and from the interior of said building and to air-condition the interior of said building. To permit an effective control of the conditions of the ambient air adjoining said sheath, each of said flow passages communicates with the ambient air adjoining said sheath through a plurality of vertically spaced apart intake openings distributed throughout the height of said sheath.