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5 条记录 (耗时 0.018 秒)

    Deposition of a conductor in a via hole or trench
    1.
    发明授权
    Deposition of a conductor in a via hole or trench 失效
    导体沉积在通孔或沟槽中

    公开(公告)号：US5918149A

    公开(公告)日：1999-06-29

    申请号：US602415

    申请日：1996-02-16

    申请人： Paul R. Besser ,  John A. Iacoponi ,  Roger Alvis

    发明人： Paul R. Besser ,  John A. Iacoponi ,  Roger Alvis

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/441

    CPC分类号： H01L21/76843 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

    摘要： The present semiconductor device and method of fabrication thereof includes the provision of a trench or via hole in a dielectric, with a barrier layer thereon extending into the trench or via hole. A layer of titanium is provided over the barrier layer, also extending into the trench or via hole, and aluminum or aluminum alloy is provided over the titanium layer. The barrier layer provides good conformal coverage while also preventing outgassing of the dielectric from adversely affecting the conductor. The barrier layer also serves as a wetting agent for the deposition and flowing of aluminum or aluminum alloy. The titanium layer can be extremely thin, or non-existent, so as to avoid significant growth of TiAl.sub.3 and the problems attendant thereto.

    摘要翻译： 本半导体器件及其制造方法包括在电介质中设置沟槽或通孔，其上的阻挡层延伸到沟槽或通孔中。 在阻挡层上设置一层钛，也延伸到沟槽或通孔中，在钛层上提供铝或铝合金。 阻挡层提供良好的保形覆盖，同时还防止电介质的除气不利地影响导体。 阻挡层还用作铝或铝合金的沉积和流动的润湿剂。 钛层可以非常薄或不存在，以避免TiAl 3的显着生长和伴随的问题。

    Temperature sensing probe for microthermometry
    2.
    发明授权
    Temperature sensing probe for microthermometry 失效
    温度传感探针，用于微热法测量

    公开(公告)号：US5713667A

    公开(公告)日：1998-02-03

    申请号：US482229

    申请日：1995-06-07

    申请人： Roger Alvis ,  Andrew N. Erickson ,  Ayesha R. Raheem Kizchery ,  Jeremias D. Romero ,  Bryan M. Tracy

    发明人： Roger Alvis ,  Andrew N. Erickson ,  Ayesha R. Raheem Kizchery ,  Jeremias D. Romero ,  Bryan M. Tracy

    IPC分类号： G01K7/01

    CPC分类号： G01Q60/58 ,  B82Y35/00 ,  G01K7/01 ,  Y10S977/875

    摘要： A diode is formed at the tip of a pointed portion of a probe of a scanning probe microscope. When the diode is forward biased, the current through the diode varies with the temperature of the diode. The magnitude of the current is an indication of the temperature of the tip of the probe. If the tip is scanned over a surface, a thermal map of the surface can be made and hot spots on the surface located. In some embodiments, the pointed portion of the probe is made of a semiconductor material (for example, silicon). A layer of a metal (for example, platinum) is made to contact the semiconductor material of the pointed portion only at the tip of the pointed portion, thereby forming a very small temperature sensing Schottky diode at the tip of the pointed portion.

    摘要翻译： 在扫描探针显微镜的探针的尖部的尖端形成二极管。 当二极管正向偏置时，通过二极管的电流随着二极管的温度而变化。 电流的大小表示探针尖端的温度。 如果尖端在表面上扫描，则可以制作表面的热图，并且表面上的热点位于。 在一些实施例中，探针的尖锐部分由半导体材料（例如硅）制成。 使一层金属（例如铂）仅在尖部的尖端与尖部的半导体材料接触，从而在尖部的尖端处形成非常小的温度感测肖特基二极管。

    Self-aligned implant energy modulation for shallow source drain extension formation
    3.
    发明授权
    Self-aligned implant energy modulation for shallow source drain extension formation 失效
    用于浅源极漏极延伸形成的自对准植入能量调制

    公开(公告)号：US5650343A

    公开(公告)日：1997-07-22

    申请号：US474301

    申请日：1995-06-07

    申请人： Scott Luning ,  Roger Alvis

    发明人： Scott Luning ,  Roger Alvis

    IPC分类号： H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265

    CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

    摘要： A process for forming shallow and/or lightly doped regions of impurity concentration adjacent to source/drain semiconductor regions in a semiconductor device. In one embodiment, the invention comprises: (a) providing a semiconductor of a first conductivity type having a first surface; (b) forming a gate structure on said first surface, the gate structure including a gate oxide layer and a polysilicon layer, and a ledge; and (c) implanting an impurity of a second conductivity type into the material and the ledge whereby a portion of the implant enters the substrate after passing through the ledge area overlying the edge of the gate and enters the substrate to a first depth below the surface, while a second portion of the implant does not pass through the ledge and enters the substrate to a depth below the surface of the substrate deeper than the first portion. In addition, an apparatus is disclosed, The apparatus may include a substrate having a surface; an insulating layer on the surface of the substrate, having a surface; a gate material layer on the surface of the insulating layer, the gate material layer having a surface; and an overhanging ledge comprised of an etchable material, having a thickness sufficient to permit at least a portion of a dopant implant to penetrate said overhanging ledge provided on the surface of the gate material layer.

    摘要翻译： 一种用于在半导体器件中形成与源极/漏极半导体区域相邻的杂质浓度的浅和/或轻掺杂区域的工艺。 在一个实施例中，本发明包括：（a）提供具有第一表面的第一导电类型的半导体; （b）在所述第一表面上形成栅极结构，所述栅极结构包括栅极氧化物层和多晶硅层，以及栅极; 并且（c）将第二导电类型的杂质注入到所述材料和所述凸缘中，从而一部分所述注入物在通过所述凸缘区域之后进入所述衬底，所述凸缘区域覆盖所述栅极的边缘并且进入所述衬底到所述表面下方的第一深度 而植入物的第二部分不通过突出部并且进入衬底至比第一部分更深的衬底表面下方的深度。 此外，公开了一种装置。该装置可以包括具有表面的基板; 在基板的表面上具有表面的绝缘层; 所述绝缘层的表面上的栅极材料层，所述栅极材料层具有表面; 以及由可蚀刻材料组成的悬垂凸缘，其具有足以允许至少一部分掺杂剂注入物穿过设置在栅极材料层的表面上的所述悬垂凸缘的厚度。

    Shallow drain extension formation by angled implantation
    5.
    发明授权
    Shallow drain extension formation by angled implantation 失效
    通过倾斜植入形成浅层延伸

    公开(公告)号：US5935867A

    公开(公告)日：1999-08-10

    申请号：US481895

    申请日：1995-06-07

    申请人： Roger Alvis ,  Scott Luning ,  Peter Griffin

    发明人： Roger Alvis ,  Scott Luning ,  Peter Griffin

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L29/7835

    摘要： A process for forming a shallow, lightly doped region in a semiconductor device. The method comprises the steps of providing a semiconductor substrate having a surface; growing an oxide layer on the substrate, the oxide having a thickness; depositing a layer of polysilicon on the oxide; patterning the polysilicon layer and the oxide layer to provide a gate structure; and implanting into the substrate a source and a drain region about the gate structure at an angle less than 90 degrees with respect to the surface of the substrate.

    摘要翻译： 一种用于在半导体器件中形成浅的，轻掺杂区域的工艺。 该方法包括提供具有表面的半导体衬底的步骤; 在衬底上生长氧化物层，氧化物具有厚度; 在氧化物上沉积多晶硅层; 图案化多晶硅层和氧化物层以提供栅极结构; 以及相对于所述衬底的表面以小于90度的角度将围绕所述栅极结构的源极和漏极区域注入到所述衬底中。