PVD-based metallization methods for fabrication of interconnections in semiconductor devices
    7.
    发明授权
    PVD-based metallization methods for fabrication of interconnections in semiconductor devices 有权
    用于制造半导体器件中的互连的基于PVD的金属化方法

    公开(公告)号:US07745332B1

    公开(公告)日:2010-06-29

    申请号:US12074168

    申请日:2008-02-29

    IPC分类号: H01L21/44

    摘要: Recessed features on a Damascene substrate are filled with metal using plasma PVD. Recessed features having widths of less than about 300 nm, e.g., between about 30-300 nm can be filled with metals (e.g., copper and aluminum), without forming voids. In one approach, the deposition is performed by exposing the substrate to a high-density plasma characterized by high fractional ionization of metal. Under these conditions, the metal is deposited within the recess, without forming large overhang at the opening of the recess. In some embodiments, the metal is deposited within the recess, while diffusion barrier material is simultaneously etched from the field region. In a second approach, recessed features are filled by performing a plurality of profiling cycles, wherein each cycle includes a net etching and a net depositing operation. Etching and depositing parameters are adjusted such that the recessed features are filled without forming overhangs and voids.

    摘要翻译: 镶嵌衬底上的凹陷特征使用等离子体PVD填充金属。 具有小于约300nm,例如约30-300nm的宽度的凹入特征可以用金属(例如铜和铝)填充,而不形成空隙。 在一种方法中,通过将衬底暴露于以金属的高分数电离为特征的高密度等离子体中来进行沉积。 在这些条件下,金属沉积在凹槽内,而不会在凹槽的开口处形成大的突出端。 在一些实施例中,金属沉积在凹槽内,同时从场区域同时蚀刻扩散阻挡材料。 在第二种方法中,通过执行多个轮廓循环来填充凹陷特征,其中每个周期包括净蚀刻和净沉积操作。 调整蚀刻和沉积参数,使得凹陷特征被填充而不形成突出端和空隙。