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公开(公告)号：US08547075B1
公开(公告)日：2013-10-01
申请号：US13155547
申请日：2011-06-08
IPC分类号： G05F1/00
CPC分类号： G05F1/56
摘要： In one embodiment, an integrated circuit (e.g., FPGA) has two voltage regulators sharing stability and filter capacitors. A switch is located between each plate of each capacitor and a common voltage reference (e.g., ground) such that one of the two voltage regulators can be selectively connected to ground via the stability and filter capacitors.
摘要翻译： 在一个实施例中，集成电路（例如，FPGA）具有共享稳定性的两个稳压器和滤波电容器。 开关位于每个电容器的每个板和公共电压基准（例如接地）之间，使得两个电压调节器之一可以经由稳定性和滤波电容器选择性地连接到地。
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公开(公告)号：US08200179B1
公开(公告)日：2012-06-12
申请号：US12637884
申请日：2009-12-15
申请人： Paulius Mosinskis , Richard Booth
发明人： Paulius Mosinskis , Richard Booth
CPC分类号： H04L25/03254 , H03F3/45183 , H03F2200/435 , H03F2200/453 , H03F2203/45244 , H03F2203/45384 , H03G1/0029 , H04L27/01
摘要： In one embodiment, a combined VGA-and-equalizer (VGA-EQ) circuit for a communication link includes a current-mode logic (“CML”) amplifier with an inductive load circuit. The CML amplifier has a gain control terminal and is operable to amplify, with an adjustable gain, a signal received at an input terminal and provide the amplified signal at an output terminal. The CML amplifier has a first gain at frequencies below a predetermined frequency value and a second gain at frequencies in a predetermined frequency range above the predetermined frequency value, wherein the second gain is higher than the first gain. The higher second gain of the VGA-EQ circuit causes a reduction in inter-symbol interference in a signal received by the receiver.
摘要翻译： 在一个实施例中，用于通信链路的组合VGA和均衡器（VGA-EQ）电路包括具有感性负载电路的电流模式逻辑（“CML”）放大器。 CML放大器具有增益控制端，并且可操作地以可调增益放大在输入端接收的信号，并在输出端提供放大信号。 CML放大器在低于预定频率值的频率下具有第一增益，并且在预定频率值以上的预定频率范围内的频率具有第二增益，其中第二增益高于第一增益。 VGA-EQ电路的较高的第二增益导致接收机接收的信号中符号间干扰的减少。
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3.发明授权公开(公告)号：US07269809B2
公开(公告)日：2007-09-11
申请号：US11159283
申请日：2005-06-22
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).
摘要翻译： 计算机辅助设计（CAD）工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计，验证和布局。 为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计：（1）数字电子集成电路元件; （2）模拟/混合信号电子集成电路元件; 和（3）光电元件（包括无源和有源光学元件）。 一旦行为逻辑设计完成，结果将被合并并共同模拟。 为电路中的每种不同类型的元件开发和验证物理布局设计。 然后将单独的物理布局共同验证，以评估整体物理设计的属性。 将共模拟的结果与协同验证的结果进行比较，在逻辑设计和/或物理布局中进行改变，直到获得所需的操作参数。 一旦产生期望的结果，则常规晶圆级制造操作被认为是提供最终产品（“磁带输出”）。
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公开(公告)号：US08164499B1
公开(公告)日：2012-04-24
申请号：US12813540
申请日：2010-06-11
IPC分类号： H03M1/00
摘要： In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF0 to an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF1-COEFF5) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.
摘要翻译： 在串行器/解串器（SerDes）接收器的示例性判决反馈均衡器（DFE）中，单个电流镜阵列由多个当前数模转换器（IDAC）功能共享。 DFE具有初始放大器级，其将初始系数COEFF0应用于输入数据信号和将附加系数（例如，COEFF1-COEFF5）应用于恢复的输出数据的不同延迟版本的（例如，五个）附加放大器级 流。 将初始和多个附加放大器级的输出相加以产生施加到时钟和数据恢复（CDR）电路的均衡数据信号。 由于均衡器功能的某些特性，可以使用单个共享电流镜阵列实现多个附加放大器级，与传统实现相比，其保留了大量的芯片面积，其中每个附加放大器级具有其自己的专用电流镜阵列。
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公开(公告)号：US20080089634A1
公开(公告)日：2008-04-17
申请号：US11973440
申请日：2007-10-09
IPC分类号： G02F1/035
CPC分类号： G02F1/2255 , G02F1/0121 , H04B10/5051 , H04B10/50575
摘要： An optical modulator is formed to include an adjustable drive arrangement for dynamically adjusting the effective length of the optical signals path(s) within the modulator. Each modulator arm is partitioned into a plurality of segments, with each segment coupled to a separate electrical signal driver. Therefore, the effective length of each modulator arm will be a function of the number of drivers that are activated for each arm at any given point in time. A feedback arrangement may be used with the plurality of drivers to dynamically adjust the operation of the modulator by measuring the extinction ratio as a function of optical power, turning “on” or “off” individual drivers accordingly.
摘要翻译： 光学调制器被形成为包括可调驱动装置，用于动态地调节调制器内的光信号路径的有效长度。 每个调制器臂被分割成多个段，每个段耦合到单独的电信号驱动器。 因此，每个调制器臂的有效长度将是在任何给定时间点为每个臂激活的驱动器的数量的函数。 反馈装置可以与多个驱动器一起使用，以通过测量作为光功率的函数的消光比来相应地“打开”或“关闭”个别驱动器来动态地调节调制器的操作。
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公开(公告)号：US08664774B1
公开(公告)日：2014-03-04
申请号：US12757087
申请日：2010-04-09
申请人： Paulius Mosinskis
发明人： Paulius Mosinskis
IPC分类号： H01L23/52
CPC分类号： H01L24/49 , H01L23/552 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2223/6611 , H01L2224/05554 , H01L2224/45144 , H01L2224/48227 , H01L2224/4909 , H01L2224/49175 , H01L2224/49433 , H01L2924/13091 , H01L2924/3011 , H01L2924/00 , H01L2924/00014
摘要： To protect victim bondwires in a packaged electronic component from crosstalk induced by noisy aggressor bondwires, shielding bondwires are configured between the victim bondwires and the aggressor bondwires. The shielding bondwires, on either side of the victim bondwires, are connected to the same reference voltage on the package side of the component and to each other on the die side of the component, e.g., via a metal connection mounted on the die. As configured in one embodiment, the shielding bondwires and metal connection form a two-dimensional Faraday cage that shields the victim bondwires from crosstalk induced by the aggressor bondwires.
摘要翻译： 为了保护封装的电子元件中的受害者电缆线免受由嘈杂的侵入者电缆线引起的串扰，屏蔽电缆线被配置在受害者绑线和侵略者电缆线之间。 在受阻电缆线的任一侧上的屏蔽粘结线例如经由安装在管芯上的金属连接件连接到部件的封装侧的相同参考电压并且在部件的裸片侧上彼此连接。 如在一个实施例中配置的，屏蔽焊丝和金属连接形成二维法拉第笼，其屏蔽受阻的焊丝与由侵蚀者焊丝引起的串扰。
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公开(公告)号：US08441292B1
公开(公告)日：2013-05-14
申请号：US12813573
申请日：2010-06-11
IPC分类号： H03L7/00
摘要： In one embodiment, multiple (serializer/deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.
摘要翻译： 在一个实施例中，通过在反序列化之前一次选择性地滑动一个或多个输入串行数据流一比特来对齐多个（串行器/解串器）SERDES通道。 在每个SERDES通道内，滑动电路通过延长对应的时钟信号的占空比的高部分，将对应的串行数据流滑移一位（即，一个单位间隔（UI））。 时钟信号的高部分使用3对1多路复用器进行扩展，其选择固定的高信号，例如高电源轨，作为中间多路复用器输出信号，无论何时在两个不同的施加时钟信号之间进行转换 另一个用户界面。 以这种方式，滑动电路可以避免由两个时钟信号之间直接切换引起的毛刺。
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公开(公告)号：US20080088354A1
公开(公告)日：2008-04-17
申请号：US11973190
申请日：2007-10-05
申请人： Paulius Mosinskis
发明人： Paulius Mosinskis
IPC分类号： G06G7/14
CPC分类号： G02F1/2255 , G02F2001/212
摘要： An AC-coupled differential drive circuit for an optical modulator is utilized, where a common “node” is defined between top (or bottom) plates of the modulator arms themselves (the “arms” of a modulator taking the form of MOS capacitors). A low pass filter is disposed between the differential driver output and the modulator's common node to provide the desired AC coupling by filtering out the DC bias voltage of the driver circuit itself without the need for a separate, external AC coupling capacitor. An independent, adjustable DC potential can then be applied to the common node, and will appear in a balanced manner across each arm of the modulator to provide the desired DC bias for the modulator independent of the DC bias of the driver circuit.
摘要翻译： 利用用于光调制器的AC耦合差分驱动电路，其中在调制器臂本身的顶部（或底部）板之间限定了共同的“节点”（以MOS电容器的形式的调制器的“臂”）。 低通滤波器设置在差分驱动器输出和调制器的公共节点之间，以通过滤除驱动器电路本身的直流偏置电压来提供所需的AC耦合，而不需要单独的外部AC耦合电容器。 然后可以将独立的，可调节的直流电位施加到公共节点，并且将以调制器的每个臂的平衡方式出现，以提供与调制器电路的直流偏压无关的调制器的期望直流偏置。
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9.发明申请公开(公告)号：US20050289490A1
公开(公告)日：2005-12-29
申请号：US11159283
申请日：2005-06-22
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).
摘要翻译： 计算机辅助设计（CAD）工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计，验证和布局。 为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计：（1）数字电子集成电路元件; （2）模拟/混合信号电子集成电路元件; 和（3）光电元件（包括无源和有源光学元件）。 一旦行为逻辑设计完成，结果将被合并并共同模拟。 为电路中的每种不同类型的元件开发和验证物理布局设计。 然后将单独的物理布局共同验证，以评估整体物理设计的属性。 将共模拟的结果与协同验证的结果进行比较，在逻辑设计和/或物理布局中进行改变，直到获得所需的操作参数。 一旦产生期望的结果，则常规晶圆级制造操作被认为是提供最终产品（“磁带输出”）。
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