-
公开(公告)号：US07207227B2
公开(公告)日：2007-04-24
申请号：US11250548
申请日：2005-10-17
IPC分类号： G01L9/16
CPC分类号： G01L9/0042 , G01L9/0055 , Y10T29/49002 , Y10T29/49004 , Y10T29/49007
摘要： In manufacturing a pressure sensor a recess that will form part of the sensor cavity is formed in a lower silicon substrate. An SOI-wafer having a monocrystalline silicon layer on top of a substrate is bonded to the lower silicon substrate closing the recess and forming the cavity. The supporting substrate of the SOI-wafer is then etched away, the portion of the monocrystalline layer located above the recess forming the sensor diaphragm. The oxide layer of the SOI-wafer here acts as an “ideal” etch stop in the case where the substrate wafer is removed by dry (plasma) or wet etching using e.g. KOH. This is due to high etch selectivity between silicon and oxide for some etch processes and it results in a diaphragm having a very accurately defined and uniform thickness. The cavity is evacuated by forming a opening to the cavity and then sealing the cavity by closing the opening using LPCVD. Sensor paths for sensing the deflection of the diaphragm are applied on the outer or inner surface of the diaphragm. The monocrystalline diphragm gives the sensor a good long-term stability. Also the sensor path can be made of monocrystalline material, this giving the sensor even better good long-term characteristics. An increased sensitivity can be obtained by making active portions of the sensor paths freely extending, unsupported by other material of the pressure sensor, by suitable etching procedures.
摘要翻译： 在制造压力传感器中，形成传感器腔的一部分的凹部形成在下硅衬底中。 在衬底顶部具有单晶硅层的SOI晶片被接合到下硅衬底上，封闭凹部并形成空腔。 然后蚀刻掉SOI晶片的支撑衬底，单晶层的部分位于形成传感器膜片的凹部之上。 SOI晶片的氧化物层在此通过干式（等离子体）或湿式蚀刻方式除去基板晶片的情况下，作为“理想的”蚀刻停止。 KOH。 这是由于在一些蚀刻工艺之间硅和氧化物之间的高蚀刻选择性，并且其导致膜具有非常精确地限定和均匀的厚度。 通过向腔体形成开口并且然后通过使用LPCVD闭合开口来密封空腔来抽空空腔。 用于感测隔膜偏转的传感器路径被施加在隔膜的外表面或内表面上。 单晶diphragm给传感器良好的长期稳定性。 此外，传感器路径也可以由单晶材料制成，这给传感器带来更好的长期特性。 传感器路径的有效部分通过适当的蚀刻程序自由延伸，不受压力传感器的其他材料支撑，可以获得增加的灵敏度。
-
公开(公告)号：US20060032039A1
公开(公告)日：2006-02-16
申请号：US11250548
申请日：2005-10-17
IPC分类号： H01S4/00
CPC分类号： G01L9/0042 , G01L9/0055 , Y10T29/49002 , Y10T29/49004 , Y10T29/49007
摘要： In manufacturing a pressure sensor a recess that will form part of the sensor cavity is formed in a lower silicon substrate. An SOI-wafer having a monocrystalline silicon layer on top of a substrate is bonded to the lower silicon substrate closing the recess and forming the cavity. The supporting substrate of the SOI-wafer is then etched away, the portion of the monocrystalline layer located above the recess forming the sensor diaphragm. The oxide layer of the SOI-wafer here acts as an “ideal” etch stop in the case where the substrate wafer is removed by dry (plasma) or wet etching using e.g. KOH. This is due to high etch selectivity between silicon and oxide for some etch processes and it results in a diaphragm having a very accurately defined and uniform thickness. The cavity is evacuated by forming a opening to the cavity and then sealing the cavity by closing the opening using LPCVD. Sensor paths for sensing the deflection of the diaphragm are applied on the outer or inner surface of the diaphragm. The monocrystalline diphragm gives the sensor a good long-term stability. Also the sensor path can be made of monocrystalline material, this giving the sensor even better good long-term characteristics. An increased sensitivity can be obtained by making active portions of the sensor paths freely extending, unsupported by other material of the pressure sensor, by suitable etching procedures.
摘要翻译： 在制造压力传感器中，形成传感器腔的一部分的凹部形成在下硅衬底中。 在衬底顶部具有单晶硅层的SOI晶片被接合到下硅衬底上，封闭凹部并形成空腔。 然后蚀刻掉SOI晶片的支撑衬底，单晶层的部分位于形成传感器膜片的凹部之上。 SOI晶片的氧化物层在此通过干式（等离子体）或湿式蚀刻方式除去基板晶片的情况下，作为“理想的”蚀刻停止。 KOH。 这是由于在一些蚀刻工艺之间硅和氧化物之间的高蚀刻选择性，并且其导致膜具有非常精确地限定和均匀的厚度。 通过向腔体形成开口并且然后通过使用LPCVD闭合开口来密封空腔来抽空空腔。 用于感测隔膜偏转的传感器路径被施加在隔膜的外表面或内表面上。 单晶diphragm给传感器良好的长期稳定性。 此外，传感器路径也可以由单晶材料制成，这给传感器带来更好的长期特性。 传感器路径的有效部分通过适当的蚀刻程序自由延伸，不受压力传感器的其他材料支撑，可以获得增加的灵敏度。
-
公开(公告)号：US06973835B2
公开(公告)日：2005-12-13
申请号：US10492612
申请日：2002-10-15
CPC分类号： G01L9/0042 , G01L9/0055 , Y10T29/49002 , Y10T29/49004 , Y10T29/49007
摘要： In manufacturing a pressure sensor a recess that will form part of the sensor cavity is formed in a lower silicon substrate. An SOI-wafer having a monocrystalline silicon layer on top of a substrate is bonded to the lower silicon substrate closing the recess and forming the cavity. The supporting substrate of the SOI-wafer is then etched away, the portion of the monocrystalline layer located above the recess forming the sensor diaphragm. The oxide layer of the SOI-wafer here acts as an “ideal” etch stop in the case where the substrate wafer is removed by dry (plasma) or wet etching using e.g. KOH. This is due to high etch selectivity between silicon and oxide for some etch processes and it results in a diaphragm having a very accurately defined and uniform thickness. The cavity is evacuated by forming a opening to the cavity and then sealing the cavity by closing the opening using LPCVD. Sensor paths for sensing the deflection of the diaphragm are applied on the outer or inner surface of the diaphragm. The monocrystalline diphragm gives the sensor a good long-term stability. Also the sensor path can be made of monocrystalline material, this giving the sensor even better good long-term characteristics. An increased sensitivity can be obtained by making active portions of the sensor paths freely extending, unsupported by other material of the pressure sensor, by suitable etching procedures.
摘要翻译： 在制造压力传感器中，形成传感器腔的一部分的凹部形成在下硅衬底中。 在衬底顶部具有单晶硅层的SOI晶片被接合到下硅衬底上，封闭凹部并形成空腔。 然后蚀刻掉SOI晶片的支撑衬底，单晶层的部分位于形成传感器膜片的凹部之上。 SOI晶片的氧化物层在此通过干式（等离子体）或湿式蚀刻方式除去基板晶片的情况下，作为“理想的”蚀刻停止。 KOH。 这是由于在一些蚀刻工艺之间硅和氧化物之间的高蚀刻选择性，并且其导致膜具有非常精确地限定和均匀的厚度。 通过向腔体形成开口并且然后通过使用LPCVD闭合开口来密封空腔来抽空空腔。 用于感测隔膜偏转的传感器路径被施加在隔膜的外表面或内表面上。 单晶diphragm给传感器良好的长期稳定性。 此外，传感器路径也可以由单晶材料制成，这给传感器带来更好的长期特性。 传感器路径的有效部分通过适当的蚀刻程序自由延伸，不受压力传感器的其他材料支撑，可以获得增加的灵敏度。
-
公开(公告)号：US20070020926A1
公开(公告)日：2007-01-25
申请号：US10550199
申请日：2004-03-22
IPC分类号： H01L21/44
CPC分类号： B81B7/0006 , H01L21/76898 , H01L23/481 , H01L2224/05573 , H01L2224/13025 , H01L2224/131 , H01L2924/00014 , H01L2924/1461 , H01L2924/014 , H01L2924/00 , H01L2224/05599
摘要： A method of making an electrical connection between a first (top) and a second (bottom) surface of a conducting or semi-conducting substrate includes creating a trench in the first surface, and establishing an insulating enclosure entirely separating a portion of the substrate, defined by the trench. Also described is a product usable as a starting substrate for the manufacture of micro-electronic and/or micro-mechanic devices, including a flat substrate of a semi-conducting or conducting material, and having a first and a second surface and at least one electrically conducting member extending through the substrate. The electrically conducting member is insulated from surrounding material of the flat substrate by a finite layer of an insulating material, and includes the same material as the substrate, i.e. it is made from the wafer material.
摘要翻译： 在导电或半导体衬底的第一（顶部）和第二（底部）表面之间形成电连接的方法包括在第一表面中形成沟槽，以及建立绝缘外壳，其将衬底的一部分完全分开， 由沟槽限定。 还描述了可用作制造微电子和/或微机械装置的起始衬底的产品，包括半导体或导电材料的平坦衬底，并且具有第一和第二表面以及至少一个 延伸穿过基底的导电构件。 导电构件通过绝缘材料的有限层与平坦基板的周围材料绝缘，并且包括与基板相同的材料，即由晶片材料制成。
-
公开(公告)号：US07560802B2
公开(公告)日：2009-07-14
申请号：US10550199
申请日：2004-03-22
IPC分类号： H01L29/40 , H01L23/52 , H01L23/48 , H01L23/488 , H01L23/485
CPC分类号： B81B7/0006 , H01L21/76898 , H01L23/481 , H01L2224/05573 , H01L2224/13025 , H01L2224/131 , H01L2924/00014 , H01L2924/1461 , H01L2924/014 , H01L2924/00 , H01L2224/05599
摘要： A method of making an electrical connection between a first (top) and a second (bottom) surface of a conducting or semi-conducting substrate includes creating a trench in the first surface, and establishing an insulating enclosure entirely separating a portion of the substrate, defined by the trench. Also described is a product usable as a starting substrate for the manufacture of micro-electronic and/or micro-mechanic devices, including a flat substrate of a semi-conducting or conducting material, and having a first and a second surface and at least one electrically conducting member extending through the substrate. The electrically conducting member is insulated from surrounding material of the flat substrate by a finite layer of an insulating material, and includes the same material as the substrate, i.e. it is made from the wafer material.
摘要翻译： 在导电或半导体衬底的第一（顶部）和第二（底部）表面之间形成电连接的方法包括在第一表面中形成沟槽，以及建立绝缘外壳，其将衬底的一部分完全分开， 由沟槽限定。 还描述了可用作制造微电子和/或微机械装置的起始衬底的产品，包括半导体或导电材料的平坦衬底，并且具有第一和第二表面以及至少一个 延伸穿过基底的导电构件。 导电构件通过绝缘材料的有限层与平坦基板的周围材料绝缘，并且包括与基板相同的材料，即由晶片材料制成。
-
公开(公告)号：US20080265192A1
公开(公告)日：2008-10-30
申请号：US12089204
申请日：2006-10-04
申请人： Lars Stenmark , Pelle Rangsten
发明人： Lars Stenmark , Pelle Rangsten
IPC分类号： F16K31/02
CPC分类号： F16K17/383 , B64G1/402 , F16K17/403 , F16K99/0038 , Y10T137/0497 , Y10T137/1639 , Y10T137/1774 , Y10T137/8122 , Y10T137/8326
摘要： An isolation valve system includes a main body (32), an actuator body (34) and a sealing membrane (307) arranged at a high pressure portion (36) of the isolation valve system. The sealing membrane mechanically attaches the actuator body to the main body. The sealing membrane further seals the high pressure portion from a low pressure portion (38). A burst plug (315) is arranged against the main body and supports the actuator body. An activation arrangement (50) is arranged for allowing an at least partial displacement of the burst plug, typically causing a phase transition. The sealing membrane is dimensioned to break when the actuator body is moved due to the displacement of the burst plug. The isolation valve system includes preferably a stack (30) of substrates (301-304) being bonded together. The substrates have micromechanical structures, which form at least the actuator body and the sealing membrane.
摘要翻译： 隔离阀系统包括设置在隔离阀系统的高压部分（36）处的主体（32），致动器主体（34）和密封膜（307）。 密封膜将致动器主体机械地附接到主体。 密封膜进一步将高压部分与低压部分（38）密封。 爆破塞（315）被布置成抵靠主体并支撑致动器主体。 激活装置（50）被布置成允许突发塞的至少部分位移，通常导致相变。 当致动器主体由于突发塞的位移而移动时，密封膜的尺寸被设计成断裂。 隔离阀系统优选地包括结合在一起的基底（301〜304）的叠层（30）。 基板具有至少形成致动器主体和密封膜的微机械结构。
-
公开(公告)号：US08141572B2
公开(公告)日：2012-03-27
申请号：US12089204
申请日：2006-10-04
申请人： Lars Stenmark , Pelle Rangsten
发明人： Lars Stenmark , Pelle Rangsten
CPC分类号： F16K17/383 , B64G1/402 , F16K17/403 , F16K99/0038 , Y10T137/0497 , Y10T137/1639 , Y10T137/1774 , Y10T137/8122 , Y10T137/8326
摘要： An isolation valve system includes a main body (32), an actuator body (34) and a sealing membrane (307) arranged at a high pressure portion (36) of the isolation valve system. The sealing membrane mechanically attaches the actuator body to the main body. The sealing membrane further seals the high pressure portion from a low pressure portion (38). A burst plug (315) is arranged against the main body and supports the actuator body. An activation arrangement (50) is arranged for allowing an at least partial displacement of the burst plug, typically causing a phase transition. The sealing membrane is dimensioned to break when the actuator body is moved due to the displacement of the burst plug. The isolation valve system includes preferably a stack (30) of substrates (301-304) being bonded together. The substrates have micromechanical structures, which form at least the actuator body and the sealing membrane.
摘要翻译： 隔离阀系统包括设置在隔离阀系统的高压部分（36）处的主体（32），致动器主体（34）和密封膜（307）。 密封膜将致动器主体机械地附接到主体。 密封膜进一步将高压部分与低压部分（38）密封。 爆破塞（315）被布置成抵靠主体并支撑致动器主体。 激活装置（50）被布置成允许突发塞的至少部分位移，通常导致相变。 当致动器主体由于突发塞的位移而移动时，密封膜的尺寸被设计成断裂。 隔离阀系统优选地包括结合在一起的衬底（301-304）的堆叠（30）。 基板具有至少形成致动器主体和密封膜的微机械结构。
-
公开(公告)号：US08395057B2
公开(公告)日：2013-03-12
申请号：US12439568
申请日：2007-09-04
申请人： Pelle Rangsten , Hakan Johansson , Johan Bejhed
发明人： Pelle Rangsten , Hakan Johansson , Johan Bejhed
CPC分类号： B82Y15/00 , B64G1/1078 , B64G1/26 , B64G1/401 , B81B7/0006 , B81B2207/092 , B81B2207/096 , F02K9/62 , F02K9/80 , F05D2250/82 , F05D2250/84 , Y10T29/49083 , Y10T29/49099 , Y10T29/49155 , Y10T29/49346 , Y10T29/49718 , Y10T29/49746
摘要： A wafer assembly (30) includes a substrate (71), in turn including a wafer (70) or a stack of wafers. The wafer assembly (30) further includes an electrical connection (32) arranged through at least a part of the substrate (71). The electrical connection (32) is made by low-resistance silicon. The electrical connection (32) is positioned in a hole (84) penetrating at least a part of the substrate (71). A surface (78) of the substrate (71) confining the hole (84) is electrically insulating. The electrical connection (32) has at least one protrusion (75), which protrudes transversally to a main extension (83) of the hole (84) and the protrusion (75) protrudes outside a minimum hole diameter (85), as projected in the main extension (83) of the hole (84). Preferably, the protrusion (75) is supported by a support surface (81) of the substrate (71). A manufacturing method is also disclosed.
摘要翻译： 晶片组件（30）包括基板（71），其又包括晶片（70）或晶片堆叠。 晶片组件（30）还包括布置成穿过基底（71）的至少一部分的电连接（32）。 电连接（32）由低电阻硅制成。 电连接（32）位于贯穿基板（71）的至少一部分的孔（84）中。 限制孔（84）的基板（71）的表面（78）是电绝缘的。 电连接（32）具有至少一个突出部（75），该突起横向突出到孔（84）的主延伸部（83），并且突起（75）突出到最小孔直径（85）的外侧，如投影在 孔（84）的主延伸部（83）。 优选地，突起（75）由衬底（71）的支撑表面（81）支撑。 还公开了一种制造方法。
-
公开(公告)号：US20110204266A1
公开(公告)日：2011-08-25
申请号：US13125453
申请日：2009-10-19
IPC分类号： F16K31/12
CPC分类号： F16K99/0001 , F16K99/0057 , F16K2099/008 , Y10T137/1812 , Y10T137/7842 , Y10T137/8122 , Y10T137/87507 , Y10T137/87555
摘要： A micromechanical pressure relief valve arrangement (10) comprises a stack of wafers (13). An active pressure relief valve (20) is realized within the stack of wafers (13). A passive pressure relief valve (30) is also realized within said stack of wafers (13), arranged in parallel to the active pressure relief valve (20). A check valve (50), also realized within the stack of wafers (13), is arranged in series with both the active pressure relief valve (20) and the passive pressure relief valve (30).
摘要翻译： 微机械压力释放阀装置（10）包括一叠晶片（13）。 在晶片堆叠（13）内实现主动减压阀（20）。 在所述堆叠的晶片（13）内还实现被动的压力释放阀（30），其平行于主动减压阀（20）布置。 在晶片堆叠（13）内实现的止回阀（50）与主动减压阀（20）和被动式压力释放阀（30）同时布置。
-
公开(公告)号：US08684034B2
公开(公告)日：2014-04-01
申请号：US13125453
申请日：2009-10-19
IPC分类号： F16K31/12
CPC分类号： F16K99/0001 , F16K99/0057 , F16K2099/008 , Y10T137/1812 , Y10T137/7842 , Y10T137/8122 , Y10T137/87507 , Y10T137/87555
摘要： A micromechanical pressure relief valve arrangement comprises a stack of wafers. An active pressure relief valve is realized within the stack of wafers. A passive pressure relief valve is also realized within the stack of wafers, arranged in parallel to the active pressure relief valve. A check valve, also realized within the stack of wafers, is arranged in series with both the active pressure relief valve and the passive pressure relief valve.
摘要翻译： 微机械压力释放阀装置包括一叠晶片。 在堆叠的晶片内实现主动减压阀。 被动的压力释放阀也被实现在平行于主动减压阀的晶片堆内。 还实现了在堆叠的晶片内的止回阀与主动减压阀和被动减压阀两者串联布置。
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.016 秒)
