公开(公告)号：US09362139B2

公开(公告)日：2016-06-07

申请号：US13130264

申请日：2009-11-19

Applicant: Thorbjörn Ebefors ,  Edvard Kälvesten ,  Tomas Bauer

Inventor： Thorbjörn Ebefors ,  Edvard Kälvesten ,  Tomas Bauer

IPC: H01L21/768 ,  H01L21/60 ,  H01L21/50 ,  B81B7/00 ,  H01L21/683 ,  H01L23/552 ,  H01L23/58 ,  H01L23/64 ,  H01L23/66 ,  H01L23/04 ,  H01L23/48 ,  H01L21/78 ,  H01L23/10 ,  H01L23/00

CPC classification number: H01L21/50 ,  B81B7/007 ,  B81B2207/095 ,  B81C1/00301 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/585 ,  H01L23/642 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29018 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/30051 ,  H01L2224/3012 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/3512

Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.

Abstract translation: 一种制造微电子和/或微机械装置的晶片级方法，其具有通过连接（通孔）的电晶片的封盖，包括以下步骤：提供具有第一和第二侧的半导体材料的第一晶片，以及 第一侧中的多个孔和/或凹部，以及在第二侧上延伸到晶片上方的阻挡结构，所述屏障包括绝缘材料（例如氧化物）和另一材料的外层的内层。 然后，将金属施加在所述孔中，以覆盖孔中的壁和孔的底部。 去除阻挡结构，并且通过晶片背面上的连接将接触提供给晶片。 粘合结构设置在晶片的所述第一侧或第二侧中的任一个上。 晶片被接合到另一个承载电子和微电子/机械部件的晶片，使得第一晶片形成覆盖第二晶片的封盖结构。 最后，将晶片单个化为单个器件。

公开(公告)号：US08592981B2

公开(公告)日：2013-11-26

申请号：US13141609

申请日：2009-12-23

Applicant: Thorbjörn Ebefors ,  Edvard Kälvesten ,  Peter Ågren ,  Niklas Svedin

Inventor： Thorbjörn Ebefors ,  Edvard Kälvesten ,  Peter Ågren ,  Niklas Svedin

IPC: H01L29/40

CPC classification number: G02B26/0833 ,  B81B7/0006 ,  B81B7/007 ,  B81B2207/092 ,  B81B2207/095 ,  G02B6/3518 ,  G02B6/3584 ,  G02B26/0841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a layered micro-electronic and/or micro-mechanic structure, comprising at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.

Abstract translation: 本发明涉及分层的微电子和/或微机械结构，其包括在导电层之间具有绝缘层的至少三个交替的导电层。 还提供了在第一外层中的通孔，所述通孔包括由穿过该层的晶片天然材料制成的绝缘导电连接，在第一外层中延伸穿过其它层并进入所述通孔的导电插塞，以便提供 通过层的导电性，以及围绕所述其它层的至少一个所选层的所述导电插塞的绝缘外壳，用于使所述插塞与所述选定层中的材料绝缘。 它还涉及微电子和/或微机械装置，其包括设置在空腔上方的可动构件，使得其可在至少一个方向上移动。 该装置具有根据本发明的分层结构。 还提供了制造这种分层MEMS结构的方法。

公开(公告)号：US20120018898A1

公开(公告)日：2012-01-26

申请号：US13141609

申请日：2009-12-23

Applicant: Thorbjörn Ebefors ,  Edvard Kälvesten ,  Peter Agren ,  Niklas Svedin

Inventor： Thorbjörn Ebefors ,  Edvard Kälvesten ,  Peter Agren ,  Niklas Svedin

IPC: H01L23/498 ,  H01L21/762 ,  H01L21/768

CPC classification number: G02B26/0833 ,  B81B7/0006 ,  B81B7/007 ,  B81B2207/092 ,  B81B2207/095 ,  G02B6/3518 ,  G02B6/3584 ,  G02B26/0841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a layered micro-electronic and/or micro-mechanic structure, comprising at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.

Abstract translation: 本发明涉及分层的微电子和/或微机械结构，其包括在导电层之间具有绝缘层的至少三个交替的导电层。 还提供了在第一外层中的通孔，所述通孔包括由穿过该层的晶片天然材料制成的绝缘导电连接，在第一外层中延伸穿过其它层并进入所述通孔的导电插塞，以便提供 通过层的导电性，以及围绕所述其它层的至少一个所选层的所述导电插塞的绝缘外壳，用于使所述插塞与所述选定层中的材料绝缘。 它还涉及微电子和/或微机械装置，其包括设置在空腔上方的可动构件，使得其可在至少一个方向上移动。 该装置具有根据本发明的分层结构。 还提供了制造这种分层MEMS结构的方法。

公开(公告)号：US07172911B2

公开(公告)日：2007-02-06

申请号：US10504714

申请日：2003-02-14

Applicant: Edvard Kälvesten ,  Thorbjörn Ebefors ,  Niklas Svedin ,  H{dot over (a)}kan Westin

Inventor： Edvard Kälvesten ,  Thorbjörn Ebefors ,  Niklas Svedin ,  H{dot over (a)}kan Westin

IPC: H01L21/00

CPC classification number: B81C1/0015 ,  B81B2201/042 ,  B81C1/00142 ,  B81C3/002 ,  B81C2201/019 ,  B81C2201/0191 ,  B81C2203/058

Abstract: A method of making a deflectable, free hanging micro structure having at least one hinge member, the method includes the steps of providing a first sacrificial wafer having a single crystalline material constituting material forming the micro structure. A second semiconductor wafer including necessary components for forming the structure in cooperation with the first wafer is provided. Finite areas of a structured bonding material is provided, on one or both of the wafers at selected locations, the finite areas defining points of connection for joining the wafers. The wafers are bonded using heat and optionally pressure. Sacrificial material is etched away from the sacrificial wafer, patterning the top wafer by lithography is performed to define the desired deflectable microstructures having hinges, and subsequently silicon etch to make the structures.

Abstract translation: 一种制造具有至少一个铰链构件的可偏转的自由悬挂微结构的方法，所述方法包括以下步骤：提供具有形成微结构的单晶材料构成材料的第一牺牲晶片。 提供了包括与第一晶片协作形成结构的必要部件的第二半导体晶片。 在选定位置的一个或两个晶片上提供结构化接合材料的有限区域，限定用于接合晶片的连接点。 使用热和任选的压力将晶片接合。 牺牲材料被蚀刻离开牺牲晶片，通过光刻来图案化顶部晶片以限定具有铰链的期望的可偏转微结构，并随后进行硅蚀刻以制造结构。

公开(公告)号：US08308960B2

公开(公告)日：2012-11-13

申请号：US12097448

申请日：2006-12-14

Applicant: Edvard Kälvesten ,  Thorbjörn Ebefors ,  Thierry Corman

Inventor： Edvard Kälvesten ,  Thorbjörn Ebefors ,  Thierry Corman

IPC: C25F3/00 ,  B44C1/22

CPC classification number: A61M37/0015 ,  A61B5/053 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150984 ,  A61M2037/003 ,  A61M2037/0046 ,  A61M2037/0053 ,  A61N1/0502 ,  A61N1/0551 ,  H01L2224/48091 ,  H01L2224/8592 ,  H01L2924/00014

Abstract: The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.

Abstract translation: 本发明在一般方面涉及在衬底上制造垂直突出元件的方法，所述元件具有包括至少一个倾斜表面的尖端和在所述基底和所述尖端之间延伸的细长主体部分。 该方法包括形成所述倾斜表面的各向异性的晶面依赖蚀刻; 以及形成所述细长主体部分的各向异性非晶面依赖蚀刻; 结合限定所述突出元件的合适的图案化工艺具有预定的基部几何形状。

公开(公告)号：US20120097733A1

公开(公告)日：2012-04-26

申请号：US13344099

申请日：2012-01-05

Applicant: Thorbjörn EBEFORS ,  Edvard KÄLVESTEN ,  Niklas SVEDIN ,  Anders ERIKSSON

Inventor： Thorbjörn EBEFORS ,  Edvard KÄLVESTEN ,  Niklas SVEDIN ,  Anders ERIKSSON

IPC: B23K20/02 ,  B23K35/14

CPC classification number: H01L23/10 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13144 ,  H01L2224/29035 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/83805 ,  H01L2224/9211 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.

Abstract translation: 一种用于接合具有单片集成部件的半导体晶片的密封和接合材料结构。 密封和接合材料设置成形成闭环的条带。 在一个晶片上提供至少两个同心密封条。 条带布置成围绕晶片上的部件以在晶片接合在一起时被密封。 条带中的材料是将半导体晶片粘合在一起的材料，并且在受到力和任选加热时密封单片集成部件。 包括与密封和结合结构结合在一起的第一基板和第二基板的单片集成电和/或机械和/或流体和/或光学装置，以及在至少一个 描述了两个晶片并施加力并且可选地加热到晶片以连接它们。

公开(公告)号：US06548322B1

公开(公告)日：2003-04-15

申请号：US09606231

申请日：2000-06-28

Applicant: Göran Stemme ,  Edvard Kälvesten

Inventor： Göran Stemme ,  Edvard Kälvesten

IPC: H01L2100

CPC classification number: G02B5/202

Abstract: Micromachining, etching and bonding techniques are employed to fabricate hermetically sealed gas-filled chambers from silicon and/or glass wafers. The hermetically sealed gas-filled chambers have precise dimensions and are filled with a preselected concentration of gas, thus rendering exceptional performance for use as an optical gas filter. The first step involves etching one or more cavities or holes in one or more glass or silicon wafers. These wafers eventually become part of a chip assembly having one or more hermetically sealed gas-filled chambers after appropriate bonding procedures. Interfaces between aligned silicon wafers are bonded using fusion bonding techniques whereas interfaces between silicon and glass wafers are bonded using anodic bonding techniques. Bonding is accomplished in an over-pressured gas-filled bonding environment that contains a selected concentration of gas which is maintained at the bonding temperature in order to encapsulate a precise concentration of the gas within the micromachined cavity.

Abstract translation: 微加工，蚀刻和粘合技术用于从硅和/或玻璃晶片制造气密密封的气体充填室。 密封的气体充气腔室具有精确的尺寸，并且填充有预选的气体浓度，从而作为光学气体过滤器具有出色的性能。 第一步涉及蚀刻一个或多个玻璃或硅晶片中的一个或多个空腔或孔。 这些晶片最终成为具有一个或多个气密密封的气体充填室的芯片组件的一部分。 使用熔接技术将对准的硅晶片之间的接口接合，而硅和玻璃晶片之间的界面使用阳极接合技术结合。 粘合是在包含选定浓度的气体的过压气体填充的接合环境中完成的，该气体保持在接合温度，以便将精细浓度的气体包封在微加工空腔内。

公开(公告)号：US08729713B2

公开(公告)日：2014-05-20

申请号：US13193313

申请日：2011-07-28

Applicant: Thorbjörn Ebefors ,  Edvard Kälvesten ,  Peter Agren ,  Niklas Svedin

Inventor： Thorbjörn Ebefors ,  Edvard Kälvesten ,  Peter Agren ,  Niklas Svedin

IPC: H01L23/48 ,  H01L27/14 ,  H01L21/30

CPC classification number: G02B26/0841 ,  B81B7/0006 ,  B81B2201/042 ,  B81B2203/04 ,  B81B2207/096 ,  G02B26/101

Abstract: A vent hole precursor structure (26) in an intermediate product for a semi-conductor device has delicate structures (27, 28), and said intermediate product has a cavity (21) with a pressure therein differing from the pressure of the surroundings. The intermediate product comprises a first wafer (20) in which there is formed a depression (21). The first wafer is bonded to a second wafer (22) comprising a device layer (23) from which the structures (27, 28) are to be made by etching. A hole or groove (26) having a predefined depth extends downwards into the device layer, such that the cavity (21) during etching is opened up before the etching procedure breaks through the device layer (23) to form the structures (27, 28).

Abstract translation: 用于半导体器件的中间产品中的通气孔前体结构（26）具有精细的结构（27,28），并且所述中间产品具有其中不同于周围压力的压力的空腔（21）。 中间产品包括其中形成有凹部（21）的第一晶片（20）。 第一晶片被结合到包括器件层（23）的第二晶片（22）上，通过蚀刻从该器件层（23）制造结构（27,28）。 具有预定深度的孔或凹槽（26）向下延伸到装置层中，使得蚀刻过程中的空腔（21）在蚀刻过程突破穿过器件层（23）之前被打开以形成结构（27,28 ）。

公开(公告)号：US07067345B2

公开(公告)日：2006-06-27

申请号：US10181146

申请日：2001-01-17

Applicant: Edvard Kälvesten ,  Göran Stemme ,  Frank Niklaus

Inventor： Edvard Kälvesten ,  Göran Stemme ,  Frank Niklaus

IPC: H01L21/30

CPC classification number: H01L25/50 ,  G01J5/02 ,  H01L21/2007 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/82 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1433 ,  Y10T156/1092

Abstract: A method of combining components to form an integrated device, wherein the components are provided on a first sacrificial wafer, and a second non-sacrificial wafer, respectively. The sacrificial wafer carries a first plurality of components and the non-sacrificial wafer carries a second plurality of components. The wafers are bonded together with an intermediate bonding material. Optionally the sacrificial wafer is thinned to a desired level. The components of the sacrificial wafer are electrically interconnected to the component(s) on the non-sacrificial wafer. Finally, optionally the intermediate bonding material is stripped away.

公开(公告)号：US09312217B2

公开(公告)日：2016-04-12

申请号：US12162599

申请日：2007-01-31

Applicant: Edvard Kälvesten ,  Tomas Bauer ,  Thorbjörn Ebefors

Inventor： Edvard Kälvesten ,  Tomas Bauer ,  Thorbjörn Ebefors

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).

Abstract translation: 本发明涉及一种通过连接（140; 192）制造具有电晶片的用于半导体工程的起始衬底晶片的方法。 它包括提供具有前侧和后侧的具有低电阻率硅基底和前侧的高电阻率材料层的晶片（110,150）。 在晶片上，在高电阻率材料层中存在低电阻率材料岛。 这些岛与硅基材料接触。 沟槽从晶片的背面蚀刻，但并不全部穿过晶片，以提供通过连接（140; 192）限定晶片的绝缘外壳。 沟槽填充有绝缘材料。 然后研磨晶片的正面以露出绝缘材料，以通过连接产生晶片。 还提供了一种用于制造集成电子电路和/或部件的晶片基板，包括具有适用于半导体工程的高电阻率顶层（122）的低电阻率硅基底（110），其特征在于具有低电阻率晶圆连接（140 ）。