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    HIGH PERFORMANCE HKMG STACK FOR GATE FIRST INTEGRATION
    1.
    发明申请
    HIGH PERFORMANCE HKMG STACK FOR GATE FIRST INTEGRATION 有权
    高性能HKMG堆栈进行第一次整合

    公开(公告)号：US20130020656A1

    公开(公告)日：2013-01-24

    申请号：US13185112

    申请日：2011-07-18

    申请人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

    发明人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/7833

    摘要： Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.

    摘要翻译： 半导体器件在功函数层与多晶硅之间形成硅化物界面。 实施例包括通过以下方式形成高k /金属栅极堆叠：在衬底上形成高k电介质层，在高k电介质层上形成功函数金属层，在功函数金属层上形成硅化物，以及形成 硅化物上的多晶硅层。 实施例包括：通过在功函数层上原位形成反应性金属层，在反应性金属层的整个上表面上原位形成a-Si层，并与形成多晶硅层同时进行退火来形成硅化物。

    Semiconductor Device with DRAM Bit Lines Made From Same Material as Gate Electrodes in Non-Memory Regions of the Device, and Methods of Making Same
    3.
    发明申请
    Semiconductor Device with DRAM Bit Lines Made From Same Material as Gate Electrodes in Non-Memory Regions of the Device, and Methods of Making Same 有权
    具有与位于非存储器区域中的栅电极相同材料的DRAM位线的半导体器件及其制造方法

    公开(公告)号：US20120280296A1

    公开(公告)日：2012-11-08

    申请号：US13099692

    申请日：2011-05-03

    申请人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    发明人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10894 ,  H01L27/10885

    摘要： Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array.

    摘要翻译： 通常，本公开涉及一种具有由与器件的非存储区域中的栅电极相同的材料制成的DRAM位线的半导体器件及其制造方法。 本文公开的一种说明性方法包括形成包括存储器阵列和逻辑区域的半导体器件。 所述方法还包括在所述存储器阵列中形成掩埋字线，并且在形成所述掩埋字线之后，执行第一公共处理操作以形成所述逻辑区域中的导电栅电极的至少一部分并且形成至少一部分 的存储器阵列中的导电位线。

    High performance HKMG stack for gate first integration
    4.
    发明授权
    High performance HKMG stack for gate first integration 有权
    高性能HKMG堆栈，用于门控第一次集成

    公开(公告)号：US08455960B2

    公开(公告)日：2013-06-04

    申请号：US13185112

    申请日：2011-07-18

    申请人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

    发明人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

    IPC分类号： H01L29/00

    CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/7833

    摘要： Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.

    摘要翻译： 半导体器件在功函数层与多晶硅之间形成硅化物界面。 实施例包括通过以下方式形成高k /金属栅极堆叠：在衬底上形成高k电介质层，在高k电介质层上形成功函数金属层，在功函数金属层上形成硅化物，以及形成 硅化物上的多晶硅层。 实施例包括：通过在功函数层上原位形成反应性金属层，在反应性金属层的整个上表面上原位形成a-Si层，并与形成多晶硅层同时进行退火来形成硅化物。

    Method of removing gate cap materials while protecting active area
    6.
    发明授权
    Method of removing gate cap materials while protecting active area 有权
    在保护有源区域的同时去除栅极盖材料的方法

    公开(公告)号：US08697557B2

    公开(公告)日：2014-04-15

    申请号：US13154521

    申请日：2011-06-07

    申请人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    发明人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    IPC分类号： H01L29/78

    CPC分类号： H01L29/6659 ,  H01L21/31053 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer.

    摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括在半导体衬底之上形成栅电极结构，其中栅电极结构包括栅极绝缘层，栅极电极，靠近栅电极定位的第一侧壁隔离物和栅极盖层，以及形成 栅极覆盖层上方的蚀刻停止层，以及靠近栅电极结构的衬底上方的蚀刻停止层。 该方法还包括在蚀刻停止层上方形成间隔物材料层，以及执行至少一个第一平面化处理以去除位于栅极电极上方的所述隔离层材料层的部分，所述蚀刻停止层的部分位于 栅电极和栅极帽层。

    Method of Removing Gate Cap Materials While Protecting Active Area
    7.
    发明申请
    Method of Removing Gate Cap Materials While Protecting Active Area 有权
    保护活动区域时取出盖帽材料的方法

    公开(公告)号：US20120313187A1

    公开(公告)日：2012-12-13

    申请号：US13154521

    申请日：2011-06-07

    申请人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    发明人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    IPC分类号： H01L29/78 ,  H01L21/3205

    CPC分类号： H01L29/6659 ,  H01L21/31053 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer.

    摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括在半导体衬底之上形成栅电极结构，其中栅电极结构包括栅极绝缘层，栅极电极，靠近栅电极定位的第一侧壁隔离物和栅极盖层，以及形成 栅极覆盖层上方的蚀刻停止层，以及靠近栅电极结构的衬底上方的蚀刻停止层。 该方法还包括在蚀刻停止层上方形成间隔物材料层，以及执行至少一个第一平面化处理以去除位于栅极电极上方的所述隔离层材料层的部分，所述蚀刻停止层的部分位于 栅电极和栅极帽层。

    Replacement gate compatible eDRAM transistor with recessed channel
    8.
    发明授权
    Replacement gate compatible eDRAM transistor with recessed channel 有权
    具有凹槽通道的替换门兼容eDRAM晶体管

    公开(公告)号：US08716077B2

    公开(公告)日：2014-05-06

    申请号：US13215635

    申请日：2011-08-23

    申请人： Till Schloesser ,  Peter Baars ,  Frank Jakubowski

    发明人： Till Schloesser ,  Peter Baars ,  Frank Jakubowski

    IPC分类号： H01L21/336 ,  H01L21/8242

    CPC分类号： H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7848

    摘要： An eDRAM is fabricated including high performance logic transistor technology and ultra low leakage DRAM transistor technology. Embodiments include forming a recessed channel in a substrate, forming a first gate oxide to a first thickness lining the channel and a second gate oxide to a second thickness over a portion of an upper surface of the substrate, forming a first polysilicon gate in the recessed channel and overlying the recessed channel, forming a second polysilicon gate on the second gate oxide, forming spacers on opposite sides of each of the first and second polysilicon gates, removing the first and second polysilicon gates forming first and second cavities, forming a high-k dielectric layer on the first and second gate oxides, and forming first and second metal gates in the first and second cavities, respectively.

    摘要翻译： 一种eDRAM被制造成包括高性能逻辑晶体管技术和超低泄漏DRAM晶体管技术。 实施例包括在衬底中形成凹陷通道，在衬底的上表面的一部分上形成第一栅极氧化物至衬底通道的第一厚度和形成第二厚度的第二栅极氧化物，在凹陷部分中形成第一多晶硅栅极 在所述第二栅极氧化物上形成第二多晶硅栅极，在所述第一和第二多晶硅栅极中的每一个的相对侧上形成间隔物，去除形成第一和第二空腔的第一和第二多晶硅栅极， k电介质层，并且分别在第一和第二空腔中形成第一和第二金属栅极。

    Semiconductor device with DRAM bit lines made from same material as gate electrodes in non-memory regions of the device, and methods of making same
    9.
    发明授权
    Semiconductor device with DRAM bit lines made from same material as gate electrodes in non-memory regions of the device, and methods of making same 有权
    具有与器件的非存储区域中的栅电极相同材料制成的DRAM位线的半导体器件及其制造方法

    公开(公告)号：US08609457B2

    公开(公告)日：2013-12-17

    申请号：US13099692

    申请日：2011-05-03

    申请人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    发明人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    IPC分类号： H01L21/00 ,  H01L21/8242

    CPC分类号： H01L27/10894 ,  H01L27/10885

    摘要： Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array.

    摘要翻译： 通常，本公开涉及一种具有由与器件的非存储区域中的栅电极相同的材料制成的DRAM位线的半导体器件及其制造方法。 本文公开的一种说明性方法包括形成包括存储器阵列和逻辑区域的半导体器件。 所述方法还包括在所述存储器阵列中形成掩埋字线，并且在形成所述掩埋字线之后，执行第一公共处理操作以形成所述逻辑区域中的导电栅电极的至少一部分并且形成至少一部分 的存储器阵列中的导电位线。