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公开(公告)号：US08045549B2
公开(公告)日：2011-10-25
申请号：US10389929
申请日：2003-03-18
IPC分类号： H04L12/28
CPC分类号： H04Q3/66 , H04L47/34 , H04Q2213/13106 , H04Q2213/13141 , H04Q2213/13166 , H04Q2213/13174 , H04Q2213/13204 , H04Q2213/13296 , H04Q2213/13298 , H04Q2213/13348 , H04Q2213/13389
摘要： A method for packet reordering in a network processor, including the steps of processing packets, dividing the processed packets into a plurality of tiers and reordering the tiers independently from each other and collecting eligible packets from the plurality of tiers in a collector for forwarding. The method further includes the step of during the processing, determining the nominal packet processing time of each packet. The processed packets are divided into the plurality of tiers depending on the nominal packet processing time.
摘要翻译： 一种网络处理器中的分组重新排序的方法，包括处理分组的步骤，将处理的分组划分成多个层，并且彼此独立地重排序层，并收集来自收集器中的多个层的合格分组以进行转发。 该方法还包括在处理期间确定每个分组的标称分组处理时间的步骤。 处理的分组根据标称分组处理时间被划分成多个层。
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公开(公告)号：US06532185B2
公开(公告)日：2003-03-11
申请号：US09792605
申请日：2001-02-23
申请人： Jean Louis Calvignac , Peter Irma August Barri , Ivan Oscar Clemminck , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Bart Joseph Gerard Pauwels , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Jean Louis Calvignac , Peter Irma August Barri , Ivan Oscar Clemminck , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Bart Joseph Gerard Pauwels , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： G11C800
CPC分类号： H04L49/901 , G06F12/0607 , H04L49/90 , H04L49/9031
摘要： Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.
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公开(公告)号：US06657962B1
公开(公告)日：2003-12-02
申请号：US09546651
申请日：2000-04-10
申请人： Peter Irma August Barri , Brian Mitchell Bass , Jean Louis Calvignac , Ivan Oscar Clemminck , Marco C. Heddes , Clark Debs Jeffries , Michael Steven Siegel , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Peter Irma August Barri , Brian Mitchell Bass , Jean Louis Calvignac , Ivan Oscar Clemminck , Marco C. Heddes , Clark Debs Jeffries , Michael Steven Siegel , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： H04L1256
CPC分类号： H04L47/2441 , H04L47/10 , H04L47/12 , H04L47/30 , H04L47/32 , H04L49/103 , H04L49/3018 , H04L49/50 , H04L49/90
摘要： A system for minimizing congestion in a communication system is disclosed. The system comprises at least one ingress system for providing data. The ingress system includes a first free queue and a first flow queue. The system also includes a first congestion adjustment module for receiving congestion indications from the free queue and the flow queue. The first congestion adjustment module generates end stores transmit probabilities and performs per packet flow control actions. The system further includes a switch fabric for receiving data from the ingress system and for providing a congestion indication to the ingress system. The system further includes at least one egress system for receiving the data from the switch fabric. The egress system includes a second free queue and a second flow queue. The system also includes a second congestion adjustment module for receiving congestion indications from the second free queue and the second flow queue. The second congestion adjustment module generates and stores transmit probabilities and performs per packet flow control actions. Finally, the system includes a scheduler for determining the order and timing of transmission of packets out the egress system and to another node or destination. A method and system in accordance with the present invention provides for a unified method and system for logical connection of congestion with the appropriate flow control responses. The method and system utilizes congestion indicators within the ingress system, egress system, and the switch fabric in conjunction with a coarse adjustment system and fine adjustment system within the ingress device and the egress device to intelligently manage the system.
摘要翻译： 公开了一种用于最小化通信系统中的拥塞的系统。 该系统包括用于提供数据的至少一个入口系统。 入口系统包括第一空闲队列和第一流队列。 该系统还包括用于从空闲队列和流队列接收拥塞指示的第一拥塞调整模块。 第一拥塞调整模块生成终端存储发送概率并执行每个分组流控制动作。 该系统还包括用于从入口系统接收数据并向入口系统提供拥塞指示的交换结构。 该系统还包括用于从交换结构接收数据的至少一个出口系统。 出口系统包括第二空闲队列和第二流队列。 该系统还包括第二拥塞调整模块，用于从第二空闲队列和第二流队列接收拥塞指示。 第二拥塞调整模块生成并存储发送概率，并执行每个分组流控制动作。 最后，该系统包括一个调度器，用于确定出口系统和另一个节点或目的地的分组传输的顺序和定时。 根据本发明的方法和系统提供了用于将拥塞与适当流控制响应逻辑连接的统一方法和系统。 该方法和系统利用入口系统，出口系统和交换结构中的拥塞指示符与入口设备和出口设备内的粗调系统和精细调整系统结合，智能地管理系统。
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4.发明授权System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories 失效从低带宽存储器维持数据管道的高带宽需求的系统和方法公开(公告)号：US07506081B2
公开(公告)日：2009-03-17
申请号：US10850219
申请日：2004-05-20
申请人： Peter Irma August Barri , Jean Louis Calvignac , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Peter Irma August Barri , Jean Louis Calvignac , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： G06F3/00
CPC分类号： G11C7/1066 , G11C7/1039 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C11/4093
摘要： A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.
摘要翻译： 网络处理器包括胖管端口和存储器子系统，其提供足够的数据以满足胖管端口的带宽要求。 存储器子系统包括被控制的多个DDR DRAM，从而从一个DDR DRAM提取数据或者同时从多个DDR DRAM中提取数据。 通过控制DDR DRAM，使得输出串行或并行提供数据，数据带宽可在宽范围内调节。 类似地，数据被串行地写入一个DDR DRAM或同时被写入多个DDR DRAM。 因此，来自相同帧的数据的缓冲器被写入或从不同的DDR DRAM中读取。
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公开(公告)号：US07827310B1
公开(公告)日：2010-11-02
申请号：US11413965
申请日：2008-04-27
IPC分类号： G06F15/16
CPC分类号： H04L61/103 , H04L29/12028 , H04L29/12226 , H04L61/2015 , H04L69/16
摘要： Verifying subscriber host connectivity is disclosed. In some embodiments, a unicast address resolution protocol (ARP) request is sent to a subscriber host, and based at least in part on whether a response to the request is received from the subscriber host, it is determined whether the subscriber host remains connected to a network.
摘要翻译： 公布了用户主机连接的验证。 在一些实施例中，单播地址解析协议（ARP）请求被发送到订户主机，并且至少部分地基于是否从订户主机接收到对请求的响应，确定订户主机是否保持连接到 一个网络。
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6.发明授权公开(公告)号：US07865576B2
公开(公告)日：2011-01-04
申请号：US11712577
申请日：2007-02-27
IPC分类号： G06F15/16 , G06F15/177 , G06F15/173
CPC分类号： H04L12/2856 , H04L12/2874 , H04L29/12226 , H04L61/2015 , H04L63/10
摘要： Managing subscriber host information is disclosed. A new or updated information about a subscriber host is received. It is determined whether the subscriber host is associated with a multi-chassis peering. If it is determined that the subscriber host is associated with a multi-chassis peering, the new or updated information is propagated to a peer chassis associated with the multi-chassis peering.
摘要翻译： 公开管理用户主机信息。 接收到关于订户主机的新的或更新的信息。 确定用户主机是否与多机架对等体相关联。 如果确定订户主机与多机架对等体相关联，则新的或更新的信息被传播到与多机架对等体相关联的对等机架。
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7.发明授权Apparatus and method for efficiently sharing memory bandwidth in a network processor 失效在网络处理器中有效共享存储器带宽的装置和方法公开(公告)号：US06757795B2
公开(公告)日：2004-06-29
申请号：US10068392
申请日：2002-02-05
申请人： Peter I. A. Barri , Jean L. Calvignac , Marco C. Heddes , Joseph F. Logan , Alex M. M. Niemegeers , Fabrice J. Verplanken , Miroslav Vrana
发明人： Peter I. A. Barri , Jean L. Calvignac , Marco C. Heddes , Joseph F. Logan , Alex M. M. Niemegeers , Fabrice J. Verplanken , Miroslav Vrana
IPC分类号： G05F1200
CPC分类号： G06F13/18 , G06F13/161
摘要： A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.
摘要翻译： 网络处理器（NP）包括允许最大限度利用存储器的控制器。 控制器包括一个内存仲裁器，用于监视NP中请求者的内存访问请求，并授予高优先级请求者每次访问存储器所请求的所有内存带宽。 如果高优先级请求者请求的存储器带宽小于全部存储器带宽，则请求的带宽和全部存储器带宽之间的差异被分配给较低优先权请求者。 通过这样做，每个存储器访问都利用了完整的存储器带宽。
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公开(公告)号：US08416691B1
公开(公告)日：2013-04-09
申请号：US11414725
申请日：2006-04-27
申请人： Ron E. Haberman , Miroslav Vrana , Joseph M. Regan , Wim Henderickx , Pierre Alfons Leonard Verhelst
发明人： Ron E. Haberman , Miroslav Vrana , Joseph M. Regan , Wim Henderickx , Pierre Alfons Leonard Verhelst
CPC分类号： H04L61/2015 , H04L12/2876 , H04L67/306 , H04L69/22
摘要： Associating hosts with subscriber and service based requirements is disclosed. An identifier is extracted from a DHCP or other network address lease communication associated with a subscriber host. The identifier is used to associate the subscriber host with a requirement that is subscriber based, service based, or both subscriber and service based. The subscriber host is included in a set of one or more subscriber hosts associated with the subscriber, the service, or both, as applicable to the requirement, and the requirement is required to be enforced collectively to the one or more subscriber hosts comprising the set.
摘要翻译： 公布了基于用户和服务的要求的主机关联。 从与用户主机相关联的DHCP或其他网络地址租用通信中提取标识符。 标识符用于将用户主机与基于订户，基于服务或基于用户和服务的要求相关联。 订户主机被包括在与订户，服务或两者相关联的一个或多个订户主机的集合中，适用于该要求，并且需要集体地对包含该集合的一个或多个订户主机强制执行该要求 。
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9.发明申请公开(公告)号：US20080183769A1
公开(公告)日：2008-07-31
申请号：US11712577
申请日：2007-02-27
IPC分类号： G06F12/00
CPC分类号： H04L12/2856 , H04L12/2874 , H04L29/12226 , H04L61/2015 , H04L63/10
摘要： Managing subscriber host information is disclosed. A new or updated information about a subscriber host is received. It is determined whether the subscriber host is associated with a multi-chassis peering. If it is determined that the subscriber host is associated with a multi-chassis peering, the new or updated information is propagated to a peer chassis associated with the multi-chassis peering.
摘要翻译： 公开管理用户主机信息。 接收到关于订户主机的新的或更新的信息。 确定用户主机是否与多机架对等体相关联。 如果确定订户主机与多机架对等体相关联，则新的或更新的信息被传播到与多机架对等体相关联的对等机架。
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公开(公告)号：US20080181196A1
公开(公告)日：2008-07-31
申请号：US11712591
申请日：2007-02-27
申请人： Joseph M. Regan , Ron E. Haberman , Miroslav Vrana
发明人： Joseph M. Regan , Ron E. Haberman , Miroslav Vrana
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L12/2856 , H04L45/22 , H04L45/245 , H04L45/28 , Y02D50/30
摘要： Aggregating links across multiple chassis is disclosed. An indication that one or more local links are to be aggregated with one or more links on another chassis is received. Coordination with the other chassis is performed, via an inter-chassis control path, to present to a downstream equipment as an aggregated group of links the one or more local links and the one or more links on the other chassis.
摘要翻译： 披露了多个机架上的聚合链路。 接收到指示一个或多个本地链路将与另一机架上的一个或多个链路聚合。 通过机架间控制路径执行与另一机架的协调，以将一个或多个本地链路和另一个机箱上的一个或多个链路作为聚合的链路组呈现给下游设备。
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