利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

12 条记录 (耗时 0.027 秒)

    Methods and apparatus for controlling exponent range in floating-point calculations
    2.
    发明授权
    Methods and apparatus for controlling exponent range in floating-point calculations 有权
    用于控制浮点运算中指数范围的方法和装置

    公开(公告)号：US06578059B1

    公开(公告)日：2003-06-10

    申请号：US09169669

    申请日：1998-10-10

    申请人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi

    发明人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi

    IPC分类号： G06F748

    CPC分类号： G06F9/3865 ,  G06F7/483 ,  G06F7/49905 ,  G06F7/49942 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30123 ,  G06F2207/382

    摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

    摘要翻译： 计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

    System and method for deferring exceptions generated during speculative execution
    3.
    发明授权
    System and method for deferring exceptions generated during speculative execution 有权
    用于推迟在投机执行期间产生的异常的系统和方法

    公开(公告)号：US06301705B1

    公开(公告)日：2001-10-09

    申请号：US09164327

    申请日：1998-10-01

    申请人： Gautam B. Doshi ,  Peter Markstein ,  Alan H. Karp ,  Jerome C. Huck ,  Glenn T. Colon-Bonet ,  Michael Morrison

    发明人： Gautam B. Doshi ,  Peter Markstein ,  Alan H. Karp ,  Jerome C. Huck ,  Glenn T. Colon-Bonet ,  Michael Morrison

    IPC分类号： G06F945

    CPC分类号： G06F9/3865 ,  G06F9/3842

    摘要： The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of evaluating the instructions of the program to determine whether the individual instructions are speculative or non-speculative, and assessing each of the speculative instructions to determine whether it generates an exception. For each of the speculative instructions that generates an exception, the method then encode a deferred exception token (DET) into an unused register value of a register of the CPU. In accordance with another aspect of the invention, a system is provided, which system includes circuitry configured to evaluate the instructions of the instruction set to determine whether the individual instructions are speculative or non-speculative. The system further includes circuitry configured to assess each of the speculative instructions to determine whether it generates an exception. Finally, the system further includes circuitry configured to encode a deferred exception token (DET) into an unused register value of a register of the (CPU.

    摘要翻译： 本发明一般涉及用于支持对包括非投机和推测指令的中央处理单元（CPU）的指令集的推测性执行的系统和方法。 根据本发明的一个方面，一种方法包括以下步骤：评估程序的指令以确定各个指令是推测性还是非推测性的，并且评估每个推测性指令以确定其是否产生异常。 对于产生异常的每个推测性指令，该方法然后将延迟异常令牌（DET）编码为CPU的寄存器的未使用的寄存器值。 根据本发明的另一方面，提供了一种系统，该系统包括被配置为评估指令集的指令以确定各个指令是推测性还是非推测性的电路。 系统还包括被配置为评估每个推测性指令以确定其是否产生异常的电路。 最后，系统还包括被配置为将延迟异常令牌（DET）编码为（CPU的）寄存器的未使用寄存器值的电路。

    Method and apparatus for correctly rounding results of division and square root computations
    4.
    发明授权
    Method and apparatus for correctly rounding results of division and square root computations 失效
    用于正确舍入除法和平方根计算结果的方法和装置

    公开(公告)号：US5671170A

    公开(公告)日：1997-09-23

    申请号：US270203

    申请日：1994-07-01

    申请人： Peter Markstein ,  Alan H. Karp

    发明人： Peter Markstein ,  Alan H. Karp

    IPC分类号： G06F7/483 ,  G06F7/52 ,  G06F7/527 ,  G06F7/535 ,  G06F7/552 ,  G06F7/38

    CPC分类号： G06F7/5525 ,  G06F7/535 ,  G06F2207/382 ,  G06F2207/5355 ,  G06F2207/5356 ,  G06F7/4873 ,  G06F7/49936 ,  G06F7/49957

    摘要： A floating point arithmetic unit for correctly rounding a quotient or a square root of high precision numbers to the floating point number closest to the exact result is disclosed. The invention is generally applicable to round results to a precision greater than that provided by the floating point hardware. Prior to rounding, the hardware within the floating point unit produces a high precision mantissa with all but the last few digits correct. The rounding technique according to the invention is then used to produce a correctly rounded result using an enhanced Tuckerman test. Unlike a conventional Tuckerman test, the enhanced Tuckerman test determines the last few ULPs for both square root and division while checking for early termination. The advantage of checking for early termination is that the computation time needed to make the rounding decision can be significantly reduced.

    摘要翻译： 公开了一种用于将高精度数字的商或平方根正确舍入到最接近精确结果的浮点数的浮点算术单元。 本发明通常适用于比由浮点硬件提供的精度更大的精度的圆形结果。 在舍入之前，浮点单位内的硬件产生高精度尾数，而所有数字的最后几位都是正确的。 然后根据本发明的舍入技术使用增强的Tuckerman测试来产生正确舍入的结果。 与传统的Tuckerman测试不同，增强的Tuckerman测试确定了平方根和分割的最后几个ULP，同时检查提前终止。 检查提前终止的优点是可以显着减少进行舍入决定所需的计算时间。

    Processor architecture having two or more floating-point status fields
    5.
    发明授权
    Processor architecture having two or more floating-point status fields 有权
    具有两个或多个浮点状态字段的处理器架构

    公开(公告)号：US06370639B1

    公开(公告)日：2002-04-09

    申请号：US09169482

    申请日：1998-10-10

    申请人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi ,  Guillermo Juan Rozas

    发明人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi ,  Guillermo Juan Rozas

    IPC分类号： G06F9312

    CPC分类号： G06F9/3865 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/3842

    摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

    摘要翻译： 计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

    Methods and apparatus for handling and storing bi-endian words in a floating-point processor
    6.
    发明授权
    Methods and apparatus for handling and storing bi-endian words in a floating-point processor 有权
    用于在浮点处理器中处理和存储双向字的方法和装置

    公开(公告)号：US06212539B1

    公开(公告)日：2001-04-03

    申请号：US09169483

    申请日：1998-10-10

    申请人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi

    发明人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi

    IPC分类号： G06F700

    CPC分类号： G06F7/768 ,  G06F7/483

    摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

    摘要翻译： 计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

    Methods and apparatus for efficient control of floating-point status register
    7.
    发明授权
    Methods and apparatus for efficient control of floating-point status register 有权
    浮点状态寄存器的有效控制方法和装置

    公开(公告)号：US6151669A

    公开(公告)日：2000-11-21

    申请号：US169481

    申请日：1998-10-10

    申请人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi ,  Guillermo Juan Rozas

    发明人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi ,  Guillermo Juan Rozas

    IPC分类号： G06F7/00 ,  G06F7/76 ,  G06F9/30 ,  G06F9/302 ,  G06F9/32 ,  G06F9/38 ,  G06F15/00

    CPC分类号： G06F9/30014 ,  G06F9/30094 ,  G06F9/3842

    摘要： A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

    摘要翻译： 计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

    Floating point arithmetic unit having logic for quad precision arithmetic
    10.
    发明授权
    Floating point arithmetic unit having logic for quad precision arithmetic 失效
    具有四精度算术逻辑的浮点运算单元

    公开(公告)号：US5631859A

    公开(公告)日：1997-05-20

    申请号：US330391

    申请日：1994-10-27

    申请人： Peter Markstein ,  Clemens Roothaan ,  Dennis Brzezinski

    发明人： Peter Markstein ,  Clemens Roothaan ,  Dennis Brzezinski

    IPC分类号： G06F7/38 ,  G06F7/00 ,  G06F7/483 ,  G06F7/57 ,  G06F7/76

    CPC分类号： G06F7/483 ,  G06F2207/382 ,  G06F7/49957

    摘要： A floating point processing system which uses a multiplier unit and an adder unit to perform properly rounded quad precision floating point arithmetic operations using double-extended hardware. The floating point processing system includes quad data muxes for converting a quantity between a quad precision representation and a two double-extended precision quantities and vice versa, wherein the sum, if added at infinite precision, of the two double-extended precision quantities is equal to the quad precision quantity. The floating point processing system further include hardware for performing arithmetic operations on double-extended precision quantities.

    摘要翻译： 一种浮点处理系统，其使用乘法器单元和加法器单元来使用双扩展硬件来执行适当的四舍五入精确的浮点运算。 浮点处理系统包括用于转换四精度表示和两个双倍扩展精度量之间的数量的四数据多路复用器，反之亦然，其中如果以无限精度添加两个双倍扩展精度量的总和相等 到四精度数量。 浮点处理系统还包括用于对双倍扩展精度量执行算术运算的硬件。