公开(公告)号：US20070096169A1

公开(公告)日：2007-05-03

申请号：US11264321

申请日：2005-11-01

申请人： Ping Mei ,  Hao Luo ,  Carl Taussig

发明人： Ping Mei ,  Hao Luo ,  Carl Taussig

IPC分类号： H01L29/80

CPC分类号： H01L27/1259 ,  H01L27/1214 ,  H01L27/1218 ,  H01L29/78603

摘要： Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD.

摘要翻译： 本发明提供一种制造薄膜器件的薄膜器件和相关方法。 例如，描述了逆变器薄膜器件的制造。 此外，在基板上设置平行隔开的导电条。 功能材料沉积在导电条上。 然后在功能材料上提供3D结构，3D结构具有多个不同的高度，限定要捆扎的导电条的第一部分的至少一个高度。 然后蚀刻3D结构和功能材料以限定设置在导电条的第一部分之上的TFD。 导电条的第一部分与TFD相邻捆扎。

公开(公告)号：US08318610B2

公开(公告)日：2012-11-27

申请号：US13172543

申请日：2011-06-29

申请人： Ping Mei ,  Hao Luo ,  Carl Taussig

发明人： Ping Mei ,  Hao Luo ,  Carl Taussig

IPC分类号： H01L21/31

CPC分类号： H01L27/1259 ,  H01L27/1214 ,  H01L27/1218 ,  H01L29/78603

摘要： Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD.

摘要翻译： 本发明提供一种制造薄膜器件的薄膜器件和相关方法。 例如，描述了逆变器薄膜器件的制造。 此外，在基板上设置平行隔开的导电条。 功能材料沉积在导电条上。 然后在功能材料上提供3D结构，3D结构具有多个不同的高度，限定要捆扎的导电条的第一部分的至少一个高度。 然后蚀刻3D结构和功能材料以限定设置在导电条的第一部分之上的TFD。 导电条的第一部分与TFD相邻捆扎。

公开(公告)号：US20110256725A1

公开(公告)日：2011-10-20

申请号：US13172543

申请日：2011-06-29

申请人： Ping Mei ,  Hao Luo ,  Carl Taussig

发明人： Ping Mei ,  Hao Luo ,  Carl Taussig

IPC分类号： H01L21/311

CPC分类号： H01L27/1259 ,  H01L27/1214 ,  H01L27/1218 ,  H01L29/78603

摘要： Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD.

摘要翻译： 本发明提供一种制造薄膜器件的薄膜器件和相关方法。 例如，描述了逆变器薄膜器件的制造。 此外，在基板上设置平行隔开的导电条。 功能材料沉积在导电条上。 然后在功能材料上提供3D结构，3D结构具有多个不同的高度，限定要捆扎的导电条的第一部分的至少一个高度。 然后蚀刻3D结构和功能材料以限定设置在导电条的第一部分之上的TFD。 导电条的第一部分与TFD相邻捆扎。

公开(公告)号：US07994509B2

公开(公告)日：2011-08-09

申请号：US11264321

申请日：2005-11-01

申请人： Ping Mei ,  Hao Luo ,  Carl Taussig

发明人： Ping Mei ,  Hao Luo ,  Carl Taussig

IPC分类号： H01L29/10

CPC分类号： H01L27/1259 ,  H01L27/1214 ,  H01L27/1218 ,  H01L29/78603

摘要： Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD.

摘要翻译： 本发明提供一种制造薄膜器件的薄膜器件和相关方法。 例如，描述了逆变器薄膜器件的制造。 此外，在基板上设置平行隔开的导电条。 功能材料沉积在导电条上。 然后在功能材料上提供3D结构，3D结构具有多个不同的高度，限定要捆扎的导电条的第一部分的至少一个高度。 然后蚀刻3D结构和功能材料以限定设置在导电条的第一部分之上的TFD。 导电条的第一部分与TFD相邻捆扎。

公开(公告)号：US20050135146A1

公开(公告)日：2005-06-23

申请号：US10739350

申请日：2003-12-19

申请人： Carl Taussig ,  Warren Jackson ,  Hao Luo

发明人： Carl Taussig ,  Warren Jackson ,  Hao Luo

IPC分类号： G11C17/14 ,  G11C5/02 ,  G11C7/00 ,  G11C8/00 ,  G11C8/10 ,  G11C11/00 ,  G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  H01L27/10

CPC分类号： G11C17/16 ,  G11C5/025 ,  G11C8/10 ,  G11C13/0023 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： An addressing circuit is operable to address one or more memory elements in a cross-point memory array. The addressing circuit includes first and second sets of address lines for addressing the cross-point memory array. The address circuit also includes pull-up and pull-down circuit elements. Both the pull-up and pull-down circuit elements and the address lines include cross-point resistive elements.

公开(公告)号：US07817129B2

公开(公告)日：2010-10-19

申请号：US11590339

申请日：2006-10-30

申请人： Warren Jackson ,  Carl Taussig ,  Hao Luo

发明人： Warren Jackson ,  Carl Taussig ,  Hao Luo

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0254 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2320/043 ,  G09G2330/08

摘要： An integrated line selection apparatus within active matrix arrays is described. The circuit includes multiple gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a gate line of multiple gate lines in a gate line driver circuit coupled to an active matrix array and a source to receive an input signal. The circuit further includes at least one address line transistor device corresponding to each gate line transistor device, each address line transistor device having a drain coupled to a gate of the corresponding gate line drive transistor device and a gate coupled to a corresponding address line, such that by asserting a predetermined combination of voltages on the plurality of address lines, a single gate line of said plurality of gate lines is selected to receive the input signal to be transmitted to a corresponding pixel within the corresponding active matrix array.

摘要翻译： 描述了有源矩阵阵列内的集成线选择装置。 该电路包括多个栅极线驱动晶体管器件，每个栅极线驱动晶体管器件具有耦合到耦合到有源矩阵阵列的栅极线驱动器电路中的多个栅极线的栅极线的漏极和用于接收输入信号的源极。 该电路还包括对应于每个栅极线晶体管器件的至少一个地址线晶体管器件，每个地址线晶体管器件具有耦合到相应的栅极线驱动晶体管器件的栅极的漏极和耦合到相应的地址线的栅极， 通过在多个地址线上确定电压的预定组合，选择所述多条栅极线的单个栅极线以接收要传输到相应的有源矩阵阵列内的对应像素的输入信号。

公开(公告)号：US06980465B2

公开(公告)日：2005-12-27

申请号：US10739350

申请日：2003-12-19

申请人： Carl Taussig ,  Warren Jackson ,  Hao Luo

发明人： Carl Taussig ,  Warren Jackson ,  Hao Luo

IPC分类号： G11C17/14 ,  G11C5/02 ,  G11C7/00 ,  G11C8/00 ,  G11C8/10 ,  G11C11/00 ,  G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  H01L27/10

CPC分类号： G11C17/16 ,  G11C5/025 ,  G11C8/10 ,  G11C13/0023 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： An addressing circuit is operable to address one or more memory elements in a cross-point memory array. The addressing circuit includes first and second sets of address lines for addressing the cross-point memory array. The address circuit also includes pull-up and pull-down circuit elements. Both the pull-up and pull-down circuit elements and the address lines include cross-point resistive elements.

摘要翻译： 寻址电路可操作以寻址交叉点存储器阵列中的一个或多个存储器元件。 寻址电路包括用于寻址交叉点存储器阵列的第一组地址线和第二组地址线。 地址电路还包括上拉和下拉电路元件。 上拉和下拉电路元件和地址线都包括交叉点电阻元件。

公开(公告)号：US20080100559A1

公开(公告)日：2008-05-01

申请号：US11590339

申请日：2006-10-30

申请人： Warren Jackson ,  Carl Taussig ,  Hao Luo

发明人： Warren Jackson ,  Carl Taussig ,  Hao Luo

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0254 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2320/043 ,  G09G2330/08

摘要： An integrated line selection apparatus within active matrix arrays is described. The circuit includes multiple gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a gate line of multiple gate lines in a gate line driver circuit coupled to an active matrix array and a source to receive an input signal. The circuit further includes at least one address line transistor device corresponding to each gate line transistor device, each address line transistor device having a drain coupled to a gate of the corresponding gate line drive transistor device and a gate coupled to a corresponding address line, such that by asserting a predetermined combination of voltages on the plurality of address lines, a single gate line of said plurality of gate lines is selected to receive the input signal to be transmitted to a corresponding pixel within the corresponding active matrix array.

摘要翻译： 描述了有源矩阵阵列内的集成线选择装置。 该电路包括多个栅极线驱动晶体管器件，每个栅极线驱动晶体管器件具有耦合到耦合到有源矩阵阵列的栅极线驱动器电路中的多个栅极线的栅极线的漏极和用于接收输入信号的源极。 该电路还包括对应于每个栅极线晶体管器件的至少一个地址线晶体管器件，每个地址线晶体管器件具有耦合到相应的栅极线驱动晶体管器件的栅极的漏极和耦合到相应的地址线的栅极， 通过在多个地址线上确定电压的预定组合，选择所述多条栅极线的单个栅极线以接收要传输到相应的有源矩阵阵列内的对应像素的输入信号。

公开(公告)号：US20060018143A1

公开(公告)日：2006-01-26

申请号：US10896163

申请日：2004-07-21

申请人： Carl Taussig ,  Richard Elder ,  Hao Luo

发明人： Carl Taussig ,  Richard Elder ,  Hao Luo

IPC分类号： G11C5/02

CPC分类号： G11C5/063

摘要： An aspect of the present invention is a logical arrangement of memory arrays. The logical arrangement includes a plurality of memory arrays deposed in a row-column configuration, a controller coupled to the plurality of memory arrays and at least one power line, at least one sense line and at least one address line coupled to the controller wherein a number of connections from the controller to the at least one power line, the at least one sense line and the at least one address line is minimized.

公开(公告)号：US20100078640A1

公开(公告)日：2010-04-01

申请号：US12243073

申请日：2008-10-01

申请人： Ping Mei ,  Hao Luo ,  Albert Hua Jeans ,  Angeles Marcia Almanza-Workman ,  Robert A. Garcia ,  Warren Jackson ,  Carl P. Taussig ,  Craig M. Perlov

发明人： Ping Mei ,  Hao Luo ,  Albert Hua Jeans ,  Angeles Marcia Almanza-Workman ,  Robert A. Garcia ,  Warren Jackson ,  Carl P. Taussig ,  Craig M. Perlov

IPC分类号： H01L27/105 ,  B29D11/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  Y10S438/942

摘要： A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.

摘要翻译： 用于平板显示器的背板的装置的制造方法包括在衬底上沉积薄膜层，形成覆盖薄膜层的3D模板，以及蚀刻3D模板和薄膜层以形成栅线和晶体管 从薄膜层。 然后可以在栅极线和晶体管上沉积绝缘或钝化层，使得可以在绝缘层上形成列或数据线。