公开(公告)号：US20050156269A1

公开(公告)日：2005-07-21

申请号：US11081908

申请日：2005-03-15

申请人： Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

发明人： Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49 ,  H01L27/095

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

公开(公告)号：US20060040491A1

公开(公告)日：2006-02-23

申请号：US10923123

申请日：2004-08-21

申请人： Yeow Lim ,  Alex See ,  Tae Lee ,  David Vigar ,  Liang Hsia ,  Kin Pey

发明人： Yeow Lim ,  Alex See ,  Tae Lee ,  David Vigar ,  Liang Hsia ,  Kin Pey

IPC分类号： H01L21/4763

CPC分类号： H01L23/528 ,  H01L21/0276 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

摘要翻译： 用于宽线槽以减少压力的方法和结构。 一种示例性实施例的方法和结构是一种互连结构，包括：包括宽线的互连。 宽线有第一个插槽。 第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。 通孔插头可以从上方或下方接触宽线。 另一个示例性实施例是双镶嵌互连结构，包括：双镶嵌形互连件，其包括通孔塞，第一槽和宽线。 宽线有第一个插槽。 第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。

公开(公告)号：US20070032026A1

公开(公告)日：2007-02-08

申请号：US11195196

申请日：2005-08-02

申请人： Kuang Ong ,  Kin Pey ,  King Chui ,  Ganesh Samudra ,  Yee Yeo ,  Yung Chong

发明人： Kuang Ong ,  Kin Pey ,  King Chui ,  Ganesh Samudra ,  Yee Yeo ,  Yung Chong

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/7624 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  Y10S438/938

摘要： A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.

摘要翻译： 已经开发了通过形成相邻的硅 - 锗源/漏区来形成用于MOSFET器件的应变沟道区的工艺。 该方法的特征在于硅 - 锗层的覆盖沉积，或硅 - 锗层在源极/漏极延伸区域的暴露部分上的选择性生长。 激光退火程序通过消耗硅 - 锗层的底部部分和下面的源极/漏极区域的顶部部分而导致硅 - 锗源极/漏极区域的形成。 通过经由激光退火形成硅 - 锗源/漏区的优化可以通过在沉积硅 - 锗层之前施加到源/漏区的暴露部分的前非晶化注入（PAI）程序来实现。 在激光退火过程之后，硅 - 锗层的未反应顶部被选择性地去除。