Power converter controller with stability compensation

    公开(公告)号:US10298110B2

    公开(公告)日:2019-05-21

    申请号:US15962131

    申请日:2018-04-25

    摘要: A switched mode power converter has an energy transfer element that delivers an output signal to a load. A power switching device coupled to the primary side of the energy transfer element regulates a transfer of energy to the load. A secondary controller is coupled to receive a feedback signal and output a pulsed signal in response thereto. A primary controller is coupled to receive the pulsed signal and output a drive signal in response thereto, the drive signal being coupled to control switching of the power switching device. A compensation circuit generates an adaptively compensated signal synchronous with the pulsed signal. The adaptively compensated signal has a parameter that is adaptively adjusted in response to a comparison of the feedback signal with a threshold reference signal. The parameter converges towards a final value that produces a desired level of the output signal.

    Introducing jitter to a switching frequency by way of modulating current limit

    公开(公告)号:US10218263B2

    公开(公告)日:2019-02-26

    申请号:US15698408

    申请日:2017-09-07

    IPC分类号: H02M3/335 H02M1/44

    摘要: A controller includes a switch controller coupled to a power switch coupled to an energy transfer element. The switch controller is coupled to receive a current sense signal representative of a drain current through the power switch. The switch controller is coupled to generate a drive signal to control switching of the power switch in response to the current sense signal and a modulated current limit signal to control a transfer of energy from an input to an output of the power converter. A control modulator is coupled to generate a first signal. A jitter modulator is coupled to generate a second signal. The second signal is a periodic signal having a modulation time period that is greater than a switching period of the drive signal. An arithmetic operator circuit is coupled to generate the modulated current limit signal in response to the first signal and the second signal.

    Reduction of audible noise in a power converter

    公开(公告)号:US10171000B2

    公开(公告)日:2019-01-01

    申请号:US15979247

    申请日:2018-05-14

    摘要: A power converter controller includes a drive circuit to generate a drive signal to control switching of a power switch. The drive circuit generates the drive signal in response to a current sense signal, a current limit signal, a frequency skip signal, and a hold signal. A current limit generator generates the current limit signal in response to a load. A frequency detection circuit generates the frequency skip signal in response to the drive signal to indicate when an intended frequency of the drive signal is within a frequency window. The current limit signal remains fixed for at least a switching cycle when the intended frequency is within the frequency window. A first latch generates the hold signal to control the current limit generator to hold the current limit signal. The first latch generates the hold signal in response to the frequency skip signal and a feedback signal.

    REDUCTION OF AUDIBLE NOISE IN A POWER CONVERTER

    公开(公告)号:US20170250613A1

    公开(公告)日:2017-08-31

    申请号:US15055337

    申请日:2016-02-26

    IPC分类号: H02M3/335 H02M1/08

    摘要: A power converter controller includes a drive circuit that generates a drive signal to switch a power switch to control a transfer of energy to an output of the power converter in response to a current sense signal, a feedback signal, and a current limit signal. A current limit generator generates the current limit signal in response to a load coupled to the output. An audible noise detection circuit generates a frequency skip signal in response to the drive signal to indicate when an intended frequency of the drive signal is within an audible noise frequency window. A state of the current limit signal fixed when the intended frequency of the drive signal is within the audible noise frequency window. A first latch generates a hold signal to control the current limit generator to hold the current limit signal in response to the frequency skip signal and the feedback signal.

    LATCHING COMPARATOR
    7.
    发明申请
    LATCHING COMPARATOR 审中-公开
    锁定比较器

    公开(公告)号:US20160013731A1

    公开(公告)日:2016-01-14

    申请号:US14858740

    申请日:2015-09-18

    IPC分类号: H02M7/06 H03K5/24

    摘要: A latching comparator includes a switching logic circuit coupled to receive a first signal from a first signal circuit, and a second signal from a second signal circuit. The switching logic circuit is further coupled to receive a latching signal that is a rectangular pulse waveform in either a first or a second state. An output circuit having an input terminal is coupled to the switching logic circuit. The input terminal of the output circuit is coupled to receive both the first and second signals to compare the first signal and second signal when the latching signal is in the first state. The input terminal of the output circuit is coupled to receive only one of the first and second signals when the latching signal is in the second state.

    摘要翻译: 闭锁比较器包括耦合以从第一信号电路接收第一信号的开关逻辑电路和来自第二信号电路的第二信号。 开关逻辑电路还被耦合以接收作为第一或第二状态中的矩形脉冲波形的锁存信号。 具有输入端的输出电路耦合到开关逻辑电路。 当锁存信号处于第一状态时,输出电路的输入端耦合以接收第一和第二信号以比较第一信号和第二信号。 当锁存信号处于第二状态时,输出电路的输入端被耦合以仅接收第一和第二信号中的一个信号。

    LOAD-SELECTIVE INPUT VOLTAGE SENSOR
    8.
    发明申请
    LOAD-SELECTIVE INPUT VOLTAGE SENSOR 有权
    负载选择性输入电压传感器

    公开(公告)号:US20140268951A1

    公开(公告)日:2014-09-18

    申请号:US13801980

    申请日:2013-03-13

    IPC分类号: H02M7/12

    摘要: A power converter controller includes a switch driver circuit coupled to generate a drive signal to control switching of a power switch to control a transfer of energy from an input of the power converter to an output of the power converter. An input sense circuit is coupled to receive an input sense signal representative of the input of a power converter. A sense enable circuit is coupled to receive the drive signal to generate a sense enable signal to control the input sense circuit in response to the drive signal. The sense enable signal is coupled to control the input sense circuit to sense the input sense signal continuously in response to a first load condition, and sense the input sense signal only during a fraction of a switching period of the power switch in response to a second load condition.

    摘要翻译: 电力转换器控制器包括开关驱动器电路,其耦合以产生驱动信号以控制功率开关的切换以控制能量从功率转换器的输入到功率转换器的输出的转移。 输入检测电路被耦合以接收表示功率转换器的输入的输入检测信号。 感测使能电路被耦合以接收驱动信号以产生感测使能信号,以响应于驱动信号来控制输入检测电路。 感测使能信号被耦合以控制输入检测电路以响应于第一负载条件连续地感测输入检测信号,并且仅在功率开关的开关周期的一小部分期间响应于第二负载条件检测输入检测信号 负载条件。

    Method and Apparatus for Programming an Anti-Fuse Element in a High-Voltage Integrated Circuit
    9.
    发明申请
    Method and Apparatus for Programming an Anti-Fuse Element in a High-Voltage Integrated Circuit 有权
    用于在高压集成电路中编程抗熔丝元件的方法和装置

    公开(公告)号:US20130058182A1

    公开(公告)日:2013-03-07

    申请号:US13656066

    申请日:2012-10-19

    IPC分类号: G11C17/16

    CPC分类号: G11C17/16

    摘要: A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power IC device. The pin is connected to a drain of a high-voltage field-effect transistor (HVFET) that drives an external load via the pin during a normal operating mode of the power IC device. The voltage pulse, which is coupled to the first capacitive plate of the anti-fuse element, has a potential sufficiently high to cause a current to flow through the anti-fuse element that destroys at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates

    摘要翻译: 用于对功率IC器件的可编程块进行编程的方法包括选择要编程的可编程块的反熔丝元件。 反熔丝元件包括由电介质层分隔开的第一和第二电容板。 然后将电压脉冲施加到功率IC器件的引脚。 该引脚连接到高电压场效应晶体管(HVFET)的漏极,在功率IC器件的正常工作模式下通过引脚驱动外部负载。 耦合到抗熔丝元件的第一电容板的电压脉冲具有足够高的电位,使电流流过反熔丝元件,破坏电介质层的至少一部分,由此电短路 第一和第二电容板

    PULSE WIDTH MODULATOR WITH TWO-WAY INTEGRATOR
    10.
    发明申请
    PULSE WIDTH MODULATOR WITH TWO-WAY INTEGRATOR 有权
    带两路积分器的脉宽调制器

    公开(公告)号:US20130027151A1

    公开(公告)日:2013-01-31

    申请号:US13647222

    申请日:2012-10-08

    IPC分类号: H03K7/08

    摘要: An example PWM includes a driver and a two-way oscillator. The oscillator includes, a first frequency adjust current source, a second frequency adjust current source, a capacitor, a switching reference and a comparator. The capacitor integrates a frequency adjust current by charging with the first frequency adjust current source. The capacitor subsequently integrates a second frequency adjust current by discharging with the second frequency adjust current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to an oscillator signal. The comparator compares the output of the switching reference with a voltage on the capacitor. The first and second frequency adjust current sources vary the first and second frequency adjust currents to vary the frequency of the PWM signal to spread energy of switching harmonics over a frequency band and to reduce EMI.

    摘要翻译: 示例性PWM包括驱动器和双向振荡器。 振荡器包括第一频率调整电流源,第二频率调节电流源,电容器,开关基准和比较器。 电容器通过与第一个频率调节电流源充电来集成频率调节电流。 电容器随后通过与第二频率调节电流源放电来积分第二频率调节电流。 开关基准响应于振荡器信号输出第一参考电压和第二参考电压。 比较器将开关基准的输出与电容上的电压进行比较。 第一和第二频率调节电流源改变第一和第二频率调节电流,以改变PWM信号的频率以扩展在频带上的开关谐波的能量并且降低EMI。