公开(公告)号：US09390931B1

公开(公告)日：2016-07-12

申请号：US14813137

申请日：2015-07-30

申请人： Powerchip Technology Corporation

发明人： Kai-Yao Shih ,  Ssu-Ting Wang ,  Chi-Kai Feng ,  Te-Yuan Yin

IPC分类号： H01L21/764 ,  H01L21/28 ,  H01L27/115 ,  H01L29/06 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7883

摘要： A manufacturing method of floating gate is disclosed. A substrate having a plurality of isolation structures is provided, and top surfaces of the isolation structures are higher than a top surface of the substrate. A first conductive layer is formed on the substrate. A sacrificial layer is formed on the first conductive layer. Parts of the sacrificial layer are removed while parts of the sacrificial layer on the first conductive layer between the isolation structures are remained. Parts of the first conductive layer are removed by using the remaining parts of the sacrificial layer as masks to form conductive structures between the adjacent isolation structures. The remaining parts of the sacrificial layer are removed. A second conductive layer is formed on the substrate and the second conductive layer electrically connects with the conductive structures. The second conductive layer and the conductive structures are patterned to form floating gates.

摘要翻译： 公开了浮栅的制造方法。 提供具有多个隔离结构的基板，并且隔离结构的顶表面高于基板的顶表面。 在基板上形成第一导电层。 牺牲层形成在第一导电层上。 除去牺牲层的部分，同时保留隔离结构之间的第一导电层上的牺牲层的部分。 通过使用牺牲层的其余部分作为掩模来去除第一导电层的部分，以在相邻隔离结构之间形成导电结构。 去除牺牲层的其余部分。 第二导电层形成在衬底上，第二导电层与导电结构电连接。 图案化第二导电层和导电结构以形成浮栅。

公开(公告)号：US20160172367A1

公开(公告)日：2016-06-16

申请号：US14601232

申请日：2015-01-21

申请人： Powerchip Technology Corporation

发明人： Kai-Yao Shih ,  Ssu-Ting Wang ,  Chi-Kai Feng ,  Tzung-Hua Ying ,  Te-Yuan Yin

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/311 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266

CPC分类号： H01L27/11548 ,  H01L21/265 ,  H01L21/266 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11543 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/66825

摘要： A method of manufacturing a non-volatile memory is provided. A substrate including a first region and a second region is provided. A first patterning process is performed to the first region, so as to form a plurality of gate stack structures in the first region. Afterwards, a first sidewall oxide layer is formed to cover sidewalls and an upper surface of each gate stack structure, and a protection layer is then formed on the first sidewall oxide layer. Next, an ion implantation process is performed to the second region, and a second patterning process is performed to the second region so as to form a plurality of gate structures. Then, a second sidewall oxide layer covering sidewalls of each gate structure is formed.

摘要翻译： 提供一种制造非易失性存储器的方法。 提供了包括第一区域和第二区域的衬底。 对第一区域执行第一图案化处理，以便在第一区域中形成多个栅叠层结构。 然后，形成第一侧壁氧化物层以覆盖每个栅极堆叠结构的侧壁和上表面，然后在第一侧壁氧化物层上形成保护层。 接下来，对第二区域进行离子注入处理，并且对第二区域进行第二图案化处理，以形成多个栅极结构。 然后，形成覆盖每个栅极结构的侧壁的第二侧壁氧化物层。

公开(公告)号：US20160336431A1

公开(公告)日：2016-11-17

申请号：US14811823

申请日：2015-07-28

申请人： Powerchip Technology Corporation

发明人： Wen-Chung Yang ,  Te-Yuan Yin ,  Ssu-Ting Wang

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

CPC分类号： H01L29/66825 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02318 ,  H01L21/0337 ,  H01L21/28273 ,  H01L21/31111 ,  H01L29/42324

摘要： A method of manufacturing a semiconductor device, which includes the steps of forming a gate stack structure made up of a floating gate, an inter-poly dielectric, a control gate and a metal layer on a substrate, forming a conformal liner on the gate stack structure, covering a mask layer on the liner, where the mask layer is lower than the metal layer so that a portion of the liner is exposed, and performing a nitridation treatment to transform the exposed liner into a nitrided liner, so that at least the portion of the metal layer in the gate stack structure is covered by the nitrided liner.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在衬底上形成由浮置栅极，多晶硅电介质，控制栅极和金属层构成的栅极堆叠结构，在栅极堆叠上形成共形衬垫 结构，覆盖衬垫上的掩模层，其中掩模层低于金属层，使得衬里的一部分暴露，并且进行氮化处理以将暴露的衬垫转变成氮化衬里，使得至少 栅堆叠结构中的金属层的一部分被氮化衬里覆盖。

公开(公告)号：US09490349B1

公开(公告)日：2016-11-08

申请号：US14811823

申请日：2015-07-28

申请人： Powerchip Technology Corporation

发明人： Wen-Chung Yang ,  Te-Yuan Yin ,  Ssu-Ting Wang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/28

CPC分类号： H01L29/66825 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02318 ,  H01L21/0337 ,  H01L21/28273 ,  H01L21/31111 ,  H01L29/42324

摘要： A method of manufacturing a semiconductor device, which includes the steps of forming a gate stack structure made up of a floating gate, an inter-poly dielectric, a control gate and a metal layer on a substrate, forming a conformal liner on the gate stack structure, covering a mask layer on the liner, where the mask layer is lower than the metal layer so that a portion of the liner is exposed, and performing a nitridation treatment to transform the exposed liner into a nitrided liner, so that at least the portion of the metal layer in the gate stack structure is covered by the nitrided liner.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在衬底上形成由浮置栅极，多晶硅电介质，控制栅极和金属层构成的栅极堆叠结构，在栅极堆叠上形成共形衬垫 结构，覆盖衬垫上的掩模层，其中掩模层低于金属层，使得衬里的一部分暴露，并且进行氮化处理以将暴露的衬垫转变成氮化衬里，使得至少 栅堆叠结构中的金属层的一部分被氮化衬里覆盖。

公开(公告)号：US09466605B2

公开(公告)日：2016-10-11

申请号：US14601232

申请日：2015-01-21

申请人： Powerchip Technology Corporation

发明人： Kai-Yao Shih ,  Ssu-Ting Wang ,  Chi-Kai Feng ,  Tzung-Hua Ying ,  Te-Yuan Yin

IPC分类号： H01L21/311 ,  H01L21/266 ,  H01L27/115 ,  H01L21/265 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L27/11548 ,  H01L21/265 ,  H01L21/266 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11543 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/66825

摘要： A method of manufacturing a non-volatile memory is provided. A substrate including a first region and a second region is provided. A first patterning process is performed to the first region, so as to form a plurality of gate stack structures in the first region. Afterwards, a first sidewall oxide layer is formed to cover sidewalls and an upper surface of each gate stack structure, and a protection layer is then formed on the first sidewall oxide layer. Next, an ion implantation process is performed to the second region, and a second patterning process is performed to the second region so as to form a plurality of gate structures. Then, a second sidewall oxide layer covering sidewalls of each gate structure is formed.

摘要翻译： 提供一种制造非易失性存储器的方法。 提供了包括第一区域和第二区域的衬底。 对第一区域执行第一图案化处理，以便在第一区域中形成多个栅叠层结构。 然后，形成第一侧壁氧化物层以覆盖每个栅极堆叠结构的侧壁和上表面，然后在第一侧壁氧化物层上形成保护层。 接下来，对第二区域进行离子注入处理，并且对第二区域进行第二图案化处理，以形成多个栅极结构。 然后，形成覆盖每个栅极结构的侧壁的第二侧壁氧化物层。

公开(公告)号：US20160111295A1

公开(公告)日：2016-04-21

申请号：US14566721

申请日：2014-12-11

申请人： Powerchip Technology Corporation

发明人： Kai-Yao Shih ,  Ssu-Ting Wang ,  Te-Yuan Yin ,  Po-Cheng Chang ,  Hsin Tai

IPC分类号： H01L21/311 ,  H01L21/308

CPC分类号： H01L21/823462 ,  H01L27/11546

摘要： A method for fabricating a semiconductor device is provided. The method includes the following steps. A substrate including a memory cell region and a peripheral region is provided, and a plurality of isolation structures are formed in the substrate. Each of the isolation structures contains an exposed portion protruding beyond the surface of the substrate. A first dielectric layer is formed on the substrate. A protective layer is formed on a sidewall of the exposed portion of each of the isolation structures. The first dielectric layer on the peripheral region is removed. A second dielectric layer is formed on the substrate of the peripheral region.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括以下步骤。 提供了包括存储单元区域和周边区域的基板，并且在基板中形成多个隔离结构。 每个隔离结构都包含突出超过衬底表面的暴露部分。 在基板上形成第一电介质层。 在每个隔离结构的暴露部分的侧壁上形成保护层。 去除外围区域上的第一介电层。 在周边区域的基板上形成第二电介质层。