公开(公告)号：US20210343674A1

公开(公告)日：2021-11-04

申请号：US16886782

申请日：2020-05-29

申请人： Powertech Technology Inc.

发明人： Jeffrey Wang ,  Jen-I Huang ,  Kun-Yung Huang

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

摘要： A semiconductor package structure includes a first redistribution layer, a plurality of conductive connectors, a chip, and an encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The first redistribution layer includes at least one conductive pattern and at least one dielectric layer stacked on each other. The conductive pattern includes a plurality of landing pads, and each of the landing pads is separated from the dielectric layer. The conductive connectors are located on the first surface. Each of the conductive connectors is corresponding to and electrically connected to one of the landing pads. The chip is located on the first surface. The chip is electrically connected to the first redistribution layer. The encapsulant encapsulates the chip and the conductive connectors. A manufacturing method of a semiconductor package structure is also provided.

公开(公告)号：US11437336B2

公开(公告)日：2022-09-06

申请号：US16886782

申请日：2020-05-29

申请人： Powertech Technology Inc.

发明人： Jeffrey Wang ,  Jen-I Huang ,  Kun-Yung Huang

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

摘要： A semiconductor package structure includes a first redistribution layer, a plurality of conductive connectors, a chip, and an encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The first redistribution layer includes at least one conductive pattern and at least one dielectric layer stacked on each other. The conductive pattern includes a plurality of landing pads, and each of the landing pads is separated from the dielectric layer. The conductive connectors are located on the first surface. Each of the conductive connectors is corresponding to and electrically connected to one of the landing pads. The chip is located on the first surface. The chip is electrically connected to the first redistribution layer. The encapsulant encapsulates the chip and the conductive connectors. A manufacturing method of a semiconductor package structure is also provided.

公开(公告)号：US20170338128A1

公开(公告)日：2017-11-23

申请号：US15585160

申请日：2017-05-02

申请人： Powertech Technology Inc.

发明人： Jen-I Huang ,  Ching-Yang Chen

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC分类号： H01L23/538 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00012

摘要： A manufacturing method of a package structure is provided. The method includes the following steps. A redistribution circuit layer is formed on a first carrier. A die is disposed on the redistribution circuit layer. An encapsulant is formed to encapsulate the die. The first carrier is removed to expose a surface of the redistribution circuit layer. A plurality of recesses are formed on the surface of the redistribution circuit layer. A plurality of conductive terminals are formed corresponding to the recesses on the redistribution circuit layer. Another manufacturing method of a package structure is also provided.

公开(公告)号：US09887148B1

公开(公告)日：2018-02-06

申请号：US15437444

申请日：2017-02-21

申请人： POWERTECH TECHNOLOGY INC.

发明人： Jen-I Huang ,  Ching-Yang Chen

IPC分类号： H01L23/04 ,  H01L23/485 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L23/485 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/15313 ,  H01L2924/1533

摘要： A fan-out semiconductor package includes a layer of adhesive covering a temporary carrier, a first redistribution layer disposed on the layer of adhesive, the first redistribution layer including a first metal layer having recessed areas. Metal pillars are plated to a first group of the recessed areas in the first metal layer. A semiconductor chip next is bonded to a second group of the recessed areas and a molding compound covers the semiconductor chip. The molding compound is then ground to expose tops of the metal pillars. A second redistribution layer including a second passivation layer adhering to the molding compound and a second metal layer covering openings exposing the tops of the metal pillars are then added.