-
公开(公告)号：US08564262B2
公开(公告)日：2013-10-22
申请号：US12944392
申请日：2010-11-11
IPC分类号： G05G1/56
摘要： Mechanisms are provided for either power gating or bypassing a voltage regulator. Responsive to receiving an asserted power gate signal to power gate the output voltage of the voltage regulator, at least one of first control circuitry power gates the output voltage of a first circuit or second control circuitry power gates the output voltage of a second circuit such that substantially no voltage to is output by the first circuit to a primary output node. Responsive to receiving an asserted bypass signal to bypass the output voltage of the voltage regulator, at least one of the first control circuitry bypasses the output voltage of the first circuit or the second control circuitry bypasses the output voltage of a second circuit such that substantially the voltage of a voltage source is output by the first circuit to the primary output node.
摘要翻译： 提供电源门控或旁路电压调节器的机制。 响应于接收到被断言的电源门信号以对所述电压调节器的输出电压进行电源门控，第一控制电路电源的至少一个功率门是第一电路或第二控制电路电路的输出电压门控第二电路的输出电压，使得 基本上没有电压被第一电路输出到主输出节点。 响应于接收断言的旁路信号以绕过电压调节器的输出电压，第一控制电路中的至少一个旁路第一电路或第二控制电路的输出电压旁路第二电路的输出电压，使得基本上 电压源的电压由第一电路输出到主输出节点。
-
2.发明授权公开(公告)号：US06946869B2
公开(公告)日：2005-09-20
申请号：US10685863
申请日：2003-10-15
申请人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
发明人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
CPC分类号： H03K19/0016
摘要： Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.
摘要翻译： 泄漏电流控制装置包括在序列中执行功能的数据路径中具有一个或多个功能的电路。 每个功能具有功率降低逻辑以激励每个相应的功能。 泄漏控制电路与功率降低逻辑相互作用，使得功能在控制序列中被激励或断电，使得数据驻留的功能被激励，并且其他功能中的至少一个没有通电。
-
公开(公告)号：US20120119717A1
公开(公告)日：2012-05-17
申请号：US12944392
申请日：2010-11-11
IPC分类号： G05F1/10
摘要： Mechanisms are provided for either power gating or bypassing a voltage regulator. Responsive to receiving an asserted power gate signal to power gate the output voltage of the voltage regulator, at least one of first control circuitry power gates the output voltage of a first circuit or second control circuitry power gates the output voltage of a second circuit such that substantially no voltage to is output by the first circuit to a primary output node. Responsive to receiving an asserted bypass signal to bypass the output voltage of the voltage regulator, at least one of the first control circuitry bypasses the output voltage of the first circuit or the second control circuitry bypasses the output voltage of a second circuit such that substantially the voltage of a voltage source is output by the first circuit to the primary output node.
摘要翻译： 提供电源门控或旁路电压调节器的机制。 响应于接收到被断言的电源门信号以对所述电压调节器的输出电压进行电源门控，第一控制电路电源的至少一个功率门是第一电路或第二控制电路电路的输出电压门控第二电路的输出电压，使得 基本上没有电压被第一电路输出到主输出节点。 响应于接收断言的旁路信号以绕过电压调节器的输出电压，第一控制电路中的至少一个旁路第一电路或第二控制电路的输出电压旁路第二电路的输出电压，使得基本上 电压源的电压由第一电路输出到主输出节点。
-
4.发明申请ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS 有权基于自适应工作负载的优化与异构电流基准设计相结合，以减轻集成电路中的电流传输限制公开(公告)号：US20140195996A1
公开(公告)日：2014-07-10
申请号：US13526252
申请日：2012-06-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
-
5.发明申请Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits 有权基于令牌的电流控制，以缓解集成电路中的当前传输限制公开(公告)号：US20140082574A1
公开(公告)日：2014-03-20
申请号：US13526153
申请日：2012-06-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F9/455 , G06F9/46 , G06F9/5044 , G06F15/177 , G06F17/5022 , G06F17/5045 , G06F2212/1041 , G06F2217/78
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
-
公开(公告)号：US08635483B2
公开(公告)日：2014-01-21
申请号：US13079842
申请日：2011-04-05
申请人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
发明人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
CPC分类号： G06F1/3243 , Y02D10/152
摘要： A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.
摘要翻译： 提供了一种自动调整电源代理架构的机制。 基于与在微处理器核心上执行的应用有关的条件集合，识别用于针对微处理器核心的一组活动中的每个活动的权重因子，从而形成一组权重因子。 使用一组活动和一组权重因子生成用电量估计值。 确定功率使用估计值是否大于识别微处理器核的最大功率使用的功率代理阈值。 响应于功率使用估计值大于功率代理阈值，一组信号被发送到与微处理器核心相关联的功率代理单元中的一个或多个片上致动器，以及与组件相关联的一组操作参数 被调整。
-
7.发明授权Guarded, multi-metric resource control for safe and efficient microprocessor management 失效保护，多度量资源控制，用于安全高效的微处理器管理公开(公告)号：US08527994B2
公开(公告)日：2013-09-03
申请号：US13024781
申请日：2011-02-10
申请人： Pradip Bose , Alper Buyuktosunoglu , Niti Madan
发明人： Pradip Bose , Alper Buyuktosunoglu , Niti Madan
IPC分类号： G06F9/46
CPC分类号： G06F11/3058 , G06F1/3206 , G06F1/3234 , G06F9/5094 , Y02D10/22
摘要： A mechanism is provided for guarded, multi-metric resource control. Monitoring is performed for an intended action to address a negative condition from a resource manager in a plurality of resource managers in the data processing system. Responsive to receiving the intended action, a determination is made as to whether the intended action will cause an additional negative condition within the data processing system. Responsive to determining that the intended action will cause the additional negative condition within the data processing system, at least one alternative action is identified to be implemented in the data processing system that addresses the negative condition while not causing any additional negative condition. The at least one alternative action is then implemented in the data processing system.
摘要翻译： 提供了一种用于保护的多度量资源控制的机制。 执行针对数据处理系统中的多个资源管理器中的资源管理器处理负面条件的预期动作的监视。 响应于接收预期的动作，确定预期动作是否将在数据处理系统内引起额外的负面情况。 响应于确定预期动作将导致数据处理系统内的附加负面条件，至少一个备选动作被识别为在不引起任何附加负面条件的情况下处理负条件的数据处理系统中实现。 然后在数据处理系统中实现至少一个备选动作。
-
8.发明授权Method and system of multi-core microprocessor power management and control via per-chiplet, programmable power modes 有权多核微处理器的功能管理和控制方法和系统，通过每小时可编程电源模式进行公开(公告)号：US08001394B2
公开(公告)日：2011-08-16
申请号：US12023536
申请日：2008-01-31
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels.
摘要翻译： 提供了一种计算机实现的方法和用于管理多核微处理器中的电力的系统。 小电流中的电源管理控制微体系结构转换包括功率设置的第一命令。 小巧包括处理器核心和相关联的存储器高速缓存。 功率管理控制微体系结构包括功率模式寄存器，功率模式调节器，转换器和微架构电源管理技术。 电源管理控制微架构根据功率设置设置微体系结构电源管理技术。 全球电源管理控制器发出第一个命令。 全局功率管理控制器可以驻留在微处理器上或者关闭。 全局功率管理控制器直接针对多个小芯片中的特定小时或多个小芯片发出命令，并且控制从总线将命令转换为专用于多个小芯片内的特定小芯片的子命令。 每个小穗可以设置为分开的功率水平。
-
公开(公告)号：US20110040994A1
公开(公告)日：2011-02-17
申请号：US12539941
申请日：2009-08-12
申请人： Jayanta Basak , Pradip Bose , Alper Buyuktosunoglu , Anita Lungu
发明人： Jayanta Basak , Pradip Bose , Alper Buyuktosunoglu , Anita Lungu
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F11/3466 , Y02D10/34
摘要： A mechanism is provided for two-level guarded predictive power gating of a set of units within the data processing system. A success determines whether a unit within the set of units is power gated during a monitoring interval. If the unit is power gated, the success monitor determines whether a count of idle cycles for the unit is below a breakeven point. If the count is above the breakeven point, the success monitor increments a success efficiency counter. If the count is below the breakeven point, the success monitor determines whether the unit needs to be woke up. If the unit needs to be woke up, the success monitor increments a harmful efficiency counter. If the value of the harmful efficiency counter is less than the value from the success efficiency counter, the success monitor enables power gating for the unit via a first-level power-gating mechanism.
摘要翻译： 提供了一种用于数据处理系统内的一组单元的两级保护预测能力门控的机制。 一个成功的确定在一个监视间隔期间该单元组内的一个单元是否电源门控。 如果该单元是电源门控，则成功监视器确定该单元的空闲周期计数是否低于盈亏平衡点。 如果计数高于盈亏平衡点，则成功监视器会增加成功效率计数器。 如果计数低于盈亏平衡点，则成功监视器确定该单元是否需要醒来。 如果单位需要醒来，成功监测器会增加一个有害的效率计数器。 如果有害效率计数器的值小于成功效率计数器的值，则成功监视器可通过一级电源门控机构对单元进行功率门控。
-
公开(公告)号：US20100268975A1
公开(公告)日：2010-10-21
申请号：US12424161
申请日：2009-04-15
IPC分类号： G06F1/26
CPC分类号： G06F11/348 , G06F11/3006 , G06F11/3024 , G06F11/3062 , G06F2201/88 , Y02D10/34
摘要： A method for estimating power consumption within a multi-core microprocessor chip is provided. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.
摘要翻译： 提供了一种用于估计多核微处理器芯片内的功耗的方法。 授权用户选择要监视的一组活动。 一组活动的每个活动的值存储在一组计数器的单独计数器中，形成一组存储的值。 该值包括计数乘以活动特有的权重因子。 该组活动被分组成子集。 将对应于每个子集中的每个活动的存储值相加，形成每个子集的总值。 每个子集的总值乘以与子集对应的因子，形成每个子集的缩放值。 将每个子集的缩放值相加，形成功率使用值。 功率管理器基于功率使用值与阈值的比较来调整单元的操作参数。
-
-
-
-
-
-
-
-
-
搜索结果
112 条记录 (耗时 0.033 秒)
