利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

39 条记录 (耗时 0.018 秒)

    Method for Forming a Graded Matching Layer Structure
    1.
    发明申请
    Method for Forming a Graded Matching Layer Structure 审中-公开
    形成渐变匹配层结构的方法

    公开(公告)号：US20130195333A1

    公开(公告)日：2013-08-01

    申请号：US13362096

    申请日：2012-01-31

    申请人： Prabhjot Singh ,  Lowell Scott Smith

    发明人： Prabhjot Singh ,  Lowell Scott Smith

    IPC分类号： G06K9/00 ,  G10K11/00 ,  B05D5/12 ,  H01L41/04

    CPC分类号： G03F7/0035 ,  B06B1/0629 ,  H01L41/183

    摘要： A method for forming a graded matching layer structure is presented. The method includes (a) depositing a first material slurry on at least a portion of a substrate, (b) spreading the first material slurry to a form a first material layer having a first determined thickness, (c) exposing the first material layer using light processed through a determined light pattern mask to form a first matching layer, and (d) repeating steps (a)-(c) with different material slurries to form the graded matching layer structure.

    摘要翻译： 提出了一种形成渐变匹配层结构的方法。 该方法包括（a）在基底的至少一部分上沉积第一材料浆料，（b）将第一材料浆料铺展成具有第一确定厚度的第一材料层，（c）使用 通过确定的光图案掩模处理光以形成第一匹配层，以及（d）用不同的材料浆料重复步骤（a） - （c）以形成渐变匹配层结构。

    Method and system for booting electronic device from NAND flash memory
    3.
    发明授权
    Method and system for booting electronic device from NAND flash memory 有权
    从NAND闪存启动电子设备的方法和系统

    公开(公告)号：US08990549B2

    公开(公告)日：2015-03-24

    申请号：US13547045

    申请日：2012-07-12

    申请人： Hemant Nautiyal ,  Nitin Gera ,  Amit Rao ,  Prabhjot Singh

    发明人： Hemant Nautiyal ,  Nitin Gera ,  Amit Rao ,  Prabhjot Singh

    IPC分类号： G06F9/44

    CPC分类号： G06F9/4408

    摘要： A method and system for booting an electronic device from a NAND flash memory includes a NAND flash controller that receives an event trigger for fetching a pre-boot code stored in the NAND flash memory. Based on the event trigger type, booting parameters are loaded into the controller including a boot frequency of the NAND flash memory. The controller searches for a good memory block in which the pre-boot code is stored by checking the first and second or the first and last pages of a memory block and fetches a portion or the entire pre-boot code based on the event trigger type at the boot frequency.

    摘要翻译： 用于从NAND闪速存储器引导电子设备的方法和系统包括NAND闪存控制器，其接收用于获取存储在NAND闪速存储器中的预引导代码的事件触发。 基于事件触发类型，引导参数被加载到控制器中，包括NAND闪存的引导频率。 控制器通过检查存储器块的第一和第二或第一页和最后一页来搜索存储预引导代码的良好存储器块，并且基于事件触发类型获取部分或整个预引导代码 在引导频率。

    Multi-modality inspection system
    6.
    发明授权
    Multi-modality inspection system 有权
    多模态检查系统

    公开(公告)号：US07840367B2

    公开(公告)日：2010-11-23

    申请号：US11946244

    申请日：2007-11-28

    申请人： Francis Howard Little ,  Yanyan Wu ,  Prabhjot Singh

    发明人： Francis Howard Little ,  Yanyan Wu ,  Prabhjot Singh

    IPC分类号： G01B11/03 ,  G06F17/00

    CPC分类号： G01B11/03 ,  G01B5/008

    摘要： An inspection artifact includes a central portion and multiple optical and coordinate measurement machine (CMM) alignment features arranged on the central portion. The optical and CMM alignment features are configured to align the coordinates for an optical or a CMM measurement system to a common coordinate system. Another inspection artifact includes a central portion and multiple computed tomography (CT) alignment features arranged on the central portion. The CT alignment features are configured to align the coordinates for a CT system to a common coordinate system.

    摘要翻译： 检查工件包括中央部分和布置在中心部分上的多个光学和坐标测量机（CMM）对准特征。 光学和CMM对准特征被配置为将光学或CMM测量系统的坐标与公共坐标系对准。 另一种检查工件包括布置在中心部分上的中心部分和多个计算机断层摄影（CT）对准特征。 CT对准特征被配置为将CT系统的坐标与公共坐标系对齐。

    Memory controller
    7.
    发明授权
    Memory controller 有权
    内存控制器

    公开(公告)号：US09355691B2

    公开(公告)日：2016-05-31

    申请号：US14318685

    申请日：2014-06-29

    申请人： Prabhjot Singh ,  Hemant Nautiyal ,  Amit Rao

    发明人： Prabhjot Singh ,  Hemant Nautiyal ,  Amit Rao

    IPC分类号： G06F13/00 ,  G11C7/10 ,  G06F13/16

    CPC分类号： G11C7/1057 ,  G06F13/1689 ,  G11C7/1066

    摘要： A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous FIFO buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. The incoming read data is qualified based on the time-stamped value of the read_enable signal plus typical access latency by counting FIFO pops. The system performs correct data sampling irrespective of propagation delays between the controller and memory. The system may be implemented in a System on a Chip (SOC) device having a synchronous communication system.

    摘要翻译： 系统提供存储器和存储器控制器之间的同步读取数据采样，存储器控制器包括异步FIFO缓冲器，并输出时钟和其他控制信号。 使用出站控制信号（例如，read_enable）来使用时钟边缘计数器对读取访问的开始进行时间戳。 通过计数FIFO弹出，基于read_enable信号的时间戳值加上典型访问延迟来限定输入读取数据。 系统执行正确的数据采样，而不管控制器和存储器之间的传播延迟。 该系统可以在具有同步通信系统的片上系统（SOC）设备中实现。

    CLOCK SIGNAL GENERATOR
    8.
    发明申请
    CLOCK SIGNAL GENERATOR 有权
    时钟信号发生器

    公开(公告)号：US20150222271A1

    公开(公告)日：2015-08-06

    申请号：US14173827

    申请日：2014-02-06

    申请人： Prabhjot Singh ,  Sachin Miglani

    发明人： Prabhjot Singh ,  Sachin Miglani

    IPC分类号： H03K21/10 ,  H03K3/037

    CPC分类号： H03K21/10 ,  H03K3/017

    摘要： A clock generator suitable for use with memory devices enables generation of memory clock signals having odd or even division ratios, an optional phase shift and a 50% duty cycle. First and second clock gate circuits receive a base clock signal and an inverted version thereof, respectively, and are both gated by the output of two comparators that are set when a value of a down counter receiving the base clock signal reaches a predetermined value. The clock gate circuits each include a multiplexer and D-type flip-flop. The output from either flip-flop, or both their outputs ‘ORed’ together, may be used as a memory clock depending on the desired division ratio and phase shift. The generator is particularly suitable for DDR memory applications that require both edges of the clock signal are evenly placed for launching data on both rising and falling edges.

    摘要翻译： 适合与存储器件一起使用的时钟发生器能够产生具有奇数或偶数分频比的可选相移和50％占空比的存储器时钟信号。 第一和第二时钟门电路分别接收基本时钟信号及其反相版本，并且当接收到基本时钟信号的递减计数器的值达到预定值时，两个比较器的输出被门控。 时钟门电路各自包括多路复用器和D型触发器。 根据所需的分频比和相移，来自触发器或其输出“输出”的输出可以一起用作存储器时钟。 该发生器特别适用于DDR存储器应用，需要时钟信号的两个边沿均匀放置以在上升沿和下降沿发射数据。