公开(公告)号：US06731567B2

公开(公告)日：2004-05-04

申请号：US10350482

申请日：2003-01-24

申请人： Pramod Acharya ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier

发明人： Pramod Acharya ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C11/4093 ,  G11C2207/107

摘要： The invention relates to a DDR memory and to a storage method for storing data in a DDR memory having a plurality of memory cells which each have a prescribed word length, in which a serial data input is used to read in serial data on a rising or falling edge of the data clock signal, and a serial-parallel converter is used to put together a prescribed number of data items from the data read in to give a prescribed number of words from data words having the prescribed word length. To make transferring the data from one synchronization area to another synchronization area, and resynchronization thereof, more reliable, the invention involves an interface memory copying the at least one data word from the serial-parallel converter upon receipt of a copy signal which is synchronous with the data block signal and outputting it to a bus upon receipt of an output signal which is synchronous with the system clock signal.

摘要翻译： 本发明涉及DDR存储器和存储方法，用于将数据存储在具有多个存储单元的DDR存储器中，每个存储器单元具有规定的字长，其中使用串行数据输入来读取串行数据上升或 数据时钟信号的下降沿和串行 - 并行转换器用于将从读取的数据中的规定数量的数据项组合在一起，以从具有规定字长的数据字中给出规定数量的字。为了传送 数据从一个同步区域到另一个同步区域，并且其再同步更可靠，本发明涉及一种接收存储器，该接口存储器在接收到与数据块信号同步的复制信号时从串行 - 并行转换器复制至少一个数据字 并在接收到与系统时钟信号同步的输出信号时将其输出到总线。

公开(公告)号：US06819624B2

公开(公告)日：2004-11-16

申请号：US10249029

申请日：2003-03-11

申请人： Pramod Acharya ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier

发明人： Pramod Acharya ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/1072 ,  H03L7/0814

摘要： Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.

摘要翻译： S-DRAM的延迟时间电路，其由高频时钟信号计时，用于产生用于通过S-DRAM的数据路径进行同步数据传输的延迟数据使能控制信号，具有至少一个可控延迟时间发生器，用于 延迟具有可调延迟时间的解码数据使能控制信号，其特征在于至少一个比较电路，该比较电路将高频时钟信号的周期时间与预定的解码时间进行比较，以及通过信号延迟电路可以被接通 比较电路的装置，以便在预定的延迟时间延迟解码的数据使能控制信号，其中当时钟信号的周期时间处于限制时间区域时，信号延迟电路被比较电路接通 位于预定的解码时间。

公开(公告)号：US06804165B2

公开(公告)日：2004-10-12

申请号：US10374657

申请日：2003-02-26

申请人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Kieser ,  Pramod Acharya

发明人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Kieser ,  Pramod Acharya

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

摘要： Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path (38) of the S-DRAM (1), having a controllable latency time generator (57) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit (60) which compares a cycle time (tcycle) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path (38), and reduces the latency time of the latency time generator (57) by the cycle time if the signal delay time of the data path (38) is greater than the cycle time (tcycle) of the clock signal (CLK)

摘要翻译： 用于产生用于通过S-DRAM的数据路径（38）进行同步数据传输的延迟数据使能信号的用于由高频时钟信号（CLK）计时的S-DRAM（1）的延迟时间电路 具有可控等待时间发生器（57），用于以可调延迟时间延迟解码的外部数据使能信号（PAR），比较电路（60）比较高频时钟的周期时间（tcycle） 信号（CLK），具有所述数据路径（38）的预定信号延迟时间，并且如果所述数据路径（38）的信号延迟时间大于所述延迟时间，则将所述等待时间发生器（57）的等待时间缩短循环时间 时钟信号（CLK）的周期时间（tcycle）

公开(公告)号：US06847581B2

公开(公告)日：2005-01-25

申请号：US10340989

申请日：2003-01-13

申请人： Pramod Acharya ,  Peter Schrögmeier ,  Stefan Dietrich ,  Christian Weis

发明人： Pramod Acharya ,  Peter Schrögmeier ,  Stefan Dietrich ,  Christian Weis

IPC分类号： H03K5/00 ,  H03K5/13 ,  G11C29/00

CPC分类号： H03K5/13 ,  H03K5/00006

摘要： An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first and second input are for receiving at least one first and second clock signal that each are derived from the control clock and that are shifted in phase with respect to one another. A third clock signal is generated from the first and second clock signals, and is at a higher frequency than the frequency of the control clock for controlling operation of the circuit. The third clock signal is output at an output. Since the frequency of the third clock signal is greater than the frequency of the control clock, the circuit can, however, be operated over its full frequency range, by using a test unit to supply a control clock at a lower frequency.

摘要翻译： 集成电路包括具有至少一个第一和第二输入的处理电路，连接到用于获得控制时钟的连接。 第一和第二输入用于接收至少一个第一和第二时钟信号，每个第一和第二时钟信号各自从控制时钟导出并相对于彼此相位移位。 第三时钟信号从第一和第二时钟信号产生，并且处于比用于控制电路的操作的控制时钟的频率更高的频率。 第三个时钟信号在输出端输出。 由于第三时钟信号的频率大于控制时钟的频率，所以可以通过使用测试单元向较低频率提供控制时钟来在其全频范围内操作该电路。

公开(公告)号：US6055184A

公开(公告)日：2000-04-25

申请号：US388046

申请日：1999-09-01

申请人： Pramod Acharya ,  Jayanta Lahiri ,  Nathan Moon

发明人： Pramod Acharya ,  Jayanta Lahiri ,  Nathan Moon

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/3445 ,  G11C16/16

摘要： A flash electrically erasable and programmable read only memory (EEPROM) having a selective parallel sector erase capability (100) is disclosed. The flash EEPROM (100) includes a number of sectors (104-0 to 104-18), each of which receives an erase voltage (VCC) by way of a source switch circuit (112-0 to 112-18). The source switch circuits (112-0 to 112-18) are each enabled by logic values stored in corresponding tag registers (114-0 to 114-18). The logic values stored by the tag registers (114-0 to 114-18) can be established by the application of particular address values (A12 to A18). The logic values of the tag registers (114-0 to 114-18) can be simultaneously reset to the same value by the application of other address values (A9).

摘要翻译： 公开了具有选择性并行扇区擦除能力（100）的闪存电可擦除和可编程只读存储器（EEPROM）。 闪存EEPROM（100）包括多个扇区（104-0至104-18），每个扇区（104-0至104-18）通过源切换电路（112-0至112-18）接收擦除电压（VCC）。 源开关电路（112-0至112-18）各自由存储在相应的标签寄存器（114-0至114-18）中的逻辑值使能。 标签寄存器（114-0至114-18）存储的逻辑值可以通过应用特定地址值（A12至A18）来建立。 标签寄存器（114-0至114-18）的逻辑值可以通过应用其他地址值（A9）同时重置为相同的值。

公开(公告)号：US20110045645A1

公开(公告)日：2011-02-24

申请号：US12913239

申请日：2010-10-27

申请人： Pramod Acharya

发明人： Pramod Acharya

IPC分类号： H01L21/8238

CPC分类号： H01L27/0207 ,  H01L27/0251 ,  H01L27/118

摘要： A cell based integrated circuit chip includes a top voltage supply rail and a bottom voltage supply rail and a plurality of metal layers defining at least one filler cell. The filler cell is formed by a first field effect transistor of a first type conductivity, typically an n-channel MOSFET. The source or drain electrodes of the n-channel MOSFET are arranged to as act as a capacitor with respect to the bottom voltage supply rail and to which at least one of the source and drain electrodes is connected. A second field effect transistor of anopposite-type conductivity to the first field effect transistor, typically a p-channel MOSFET, is also provided. The source or drain electrodes of the p-channel MOSFET are connected in series between the top voltage supply rail and a gate electrode of the n-channel MOSFET. The gate electrode of the p-channel MOSFET is connected to a source of ground potential via a resistor.

摘要翻译： 基于电池的集成电路芯片包括顶部电压供应轨道和底部电压供应轨道以及限定至少一个填充单元的多个金属层。 填充单元由第一类型导电的第一场效应晶体管，通常为n沟道MOSFET形成。 n沟道MOSFET的源极或漏极被布置成相对于底部电压供应轨道作为电容器起作用，并且源极和漏极电极中的至少一个被连接到该电极。 还提供了对第一场效应晶体管（通常为p沟道MOSFET）的非对称型导电性的第二场效应晶体管。 p沟道MOSFET的源极或漏极电极串联连接在顶部电源电源轨和n沟道MOSFET的栅电极之间。 p沟道MOSFET的栅极通过电阻连接到地电位源。

公开(公告)号：US20060202724A1

公开(公告)日：2006-09-14

申请号：US11341845

申请日：2006-01-30

申请人： Pramod Acharya

发明人： Pramod Acharya

IPC分类号： H03B1/00

CPC分类号： G11C7/225 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： The invention relates to a semi-conductor component with a comparator circuit assembly (1), as well as a comparator circuit assembly (1), in particular a comparator/receiver circuit assembly, comprising a first and second transistor (8, 9), whose control inputs are connected with each other, and a third transistor (10), to whose control input an input signal (VIN) is applied, and which is connected to the first transistor (8), and a fourth transistor (11), to whose control input a reference signal (VREFmod, VER) is applied, and which is connected to the second transistor (9), whereby the control input of the third transistor (10) is connected to the control inputs of the first and second transistor (8, 9) via a coupling device (22).

摘要翻译： 本发明涉及具有比较器电路组件（1）的半导体部件，以及包括第一和第二晶体管（8,9）的比较器电路组件（1），特别是比较器/接收器电路组件， 以及第三晶体管（10），其控制输入端施加输入信号（VIN），并连接到所述第一晶体管（8），以及第四晶体管（11），其中， 其控制输入端施加参考信号（VREFmod，VER），并连接到第二晶体管（9），由此第三晶体管（10）的控制输入端连接到第一和第二晶体管 （8,9）经由联接装置（22）。

公开(公告)号：US06489759B1

公开(公告)日：2002-12-03

申请号：US09716901

申请日：2000-11-20

申请人： Pramod Acharya ,  Andreas Täuber

发明人： Pramod Acharya ,  Andreas Täuber

IPC分类号： G05F112

CPC分类号： G05F1/46

摘要： The voltage supply provides voltages to an electronic circuit requiring at least two different supply voltages. A plurality of standby supply voltages with different levels are obtained from the highest supply voltage with the aid of a voltage divider.

摘要翻译： 电压电源为需要至少两个不同电源电压的电子电路提供电压。 借助于分压器，从最高电源电压获得具有不同电平的多个备用电源电压。

公开(公告)号：US08124469B2

公开(公告)日：2012-02-28

申请号：US12913239

申请日：2010-10-27

申请人： Pramod Acharya

发明人： Pramod Acharya

IPC分类号： H01L21/8238

CPC分类号： H01L27/0207 ,  H01L27/0251 ,  H01L27/118

摘要： A cell based integrated circuit chip includes a top voltage supply rail and a bottom voltage supply rail and a plurality of metal layers defining at least one filler cell. The filler cell is formed by a first field effect transistor of a first type conductivity, typically an n-channel MOSFET. The source or drain electrodes of the n-channel MOSFET are arranged to as act as a capacitor with respect to the bottom voltage supply rail and to which at least one of the source and drain electrodes is connected. A second field effect transistor of an opposite-type conductivity to the first field effect transistor, typically a p-channel MOSFET, is also provided. The source or drain electrodes of the p-channel MOSFET are connected in series between the top voltage supply rail and a gate electrode of the n-channel MOSFET. The gate electrode of the p-channel MOSFET is connected to a source of ground potential via a resistor.

摘要翻译： 基于电池的集成电路芯片包括顶部电压供应轨道和底部电压供应轨道以及限定至少一个填充单元的多个金属层。 填充单元由第一类型导电的第一场效应晶体管，通常为n沟道MOSFET形成。 n沟道MOSFET的源极或漏极被布置成相对于底部电压供应轨道作为电容器起作用，并且源极和漏极电极中的至少一个被连接到该电极。 还提供了与第一场效应晶体管（通常为p沟道MOSFET）相反导电性的第二场效应晶体管。 p沟道MOSFET的源极或漏极电极串联连接在顶部电源电源轨和n沟道MOSFET的栅电极之间。 p沟道MOSFET的栅极通过电阻连接到地电位源。

公开(公告)号：US07888706B2

公开(公告)日：2011-02-15

申请号：US11444128

申请日：2006-05-31

申请人： Pramod Acharya

发明人： Pramod Acharya

IPC分类号： H01L27/10

CPC分类号： H01L27/0207 ,  H01L27/0251 ,  H01L27/118

摘要： A cell based integrated circuit chip includes a top voltage supply rail and a bottom voltage supply rail and a plurality of metal layers defining at least one filler cell. The filler cell is formed by a first field effect transistor of a first type conductivity, typically an n-channel MOSFET. The source or drain electrodes of the n-channel MOSFET are arranged to as act as a capacitor with respect to the bottom voltage supply rail and to which at least one of the source and drain electrodes is connected. A second field effect transistor of an opposite-type conductivity to the first field effect transistor, typically a p-channel MOSFET, is also provided. The source or drain electrodes of the p-channel MOSFET are connected in series between the top voltage supply rail and a gate electrode of the n-channel MOSFET. The gate electrode of the p-channel MOSFET is connected to a source of ground potential via a resistor.

摘要翻译： 基于电池的集成电路芯片包括顶部电压供应轨道和底部电压供应轨道以及限定至少一个填充单元的多个金属层。 填充单元由第一类型导电的第一场效应晶体管，通常为n沟道MOSFET形成。 n沟道MOSFET的源极或漏极被布置成相对于底部电压供应轨道作为电容器起作用，并且源极和漏极电极中的至少一个被连接到该电极。 还提供了与第一场效应晶体管（通常为p沟道MOSFET）相反导电性的第二场效应晶体管。 p沟道MOSFET的源极或漏极电极串联连接在顶部电源电源轨和n沟道MOSFET的栅电极之间。 p沟道MOSFET的栅极通过电阻连接到地电位源。