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公开(公告)号：US09419635B2
公开(公告)日：2016-08-16
申请号：US14343932
申请日：2012-09-10
CPC分类号： H03M1/002 , G01B11/24 , G01T1/1647 , G04F10/005 , H04N5/378 , H04N13/20 , H04N2213/001
摘要： 3D imager including at least one pixel, each pixel including a photodetector for detecting photon incidence and a time-to-digital converter system configured for referencing the photon incidence to a reference clock, and further including a reference clock generator provided for generating the reference clock, wherein the reference clock generator is configured for adjusting the frequency of the reference clock on the basis of an estimated time up to a subsequent photon incidence.
摘要翻译： 3D成像器包括至少一个像素，每个像素包括用于检测光子入射的光电检测器和配置用于参考光子入射到参考时钟的时间数字转换器系统，并且还包括参考时钟发生器，用于产生参考时钟 ，其中所述参考时钟发生器被配置为基于直到随后的光子入射的估计时间来调整所述参考时钟的频率。
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公开(公告)号：US10079608B2
公开(公告)日：2018-09-18
申请号：US14343941
申请日：2012-09-10
CPC分类号： H03M1/002 , G01B11/24 , G01T1/1647 , G04F10/005 , H04N5/378 , H04N13/20 , H04N2213/001
摘要： Time-to-digital converter system including: an event detector configured for detecting an event and generating an event detection signal upon detection of the event; and a time-to-digital converter coupled or connectable to the event detector and including a fine resolution part configured for counting fine time intervals, organized such that the fine resolution part is activated in response to the event detection signal and deactivated in response to a reference clock. 3D imager including an array of pixels, with in each pixel such a time-to-digital converter system, and further including a reference clock generator.
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公开(公告)号：US20140232827A1
公开(公告)日：2014-08-21
申请号：US14343941
申请日：2012-09-10
CPC分类号： H03M1/002 , G01B11/24 , G01T1/1647 , G04F10/005 , H04N5/378 , H04N13/20 , H04N2213/001
摘要： Time-to-digital converter system including: an event detector configured for detecting an event and generating an event detection signal upon detection of the event; and a time-to-digital converter coupled or connectable to the event detector and including a fine resolution part configured for counting fine time intervals, organized such that the fine resolution part is activated in response to the event detection signal and deactivated in response to a reference clock. 3D imager including an array of pixels, with in each pixel such a time-to-digital converter system, and further including a reference clock generator.
摘要翻译： 时间到数字转换器系统，包括：事件检测器，被配置为在检测到事件时检测事件并产生事件检测信号; 以及时间数字转换器，其耦合或连接到所述事件检测器，并且包括配置用于对精细时间间隔进行计数的精细分辨率部分，被组织成使得精细分辨率部分响应于事件检测信号被激活并且响应于 参考时钟。 3D成像器包括像素阵列，每个像素如时间 - 数字转换器系统，并且还包括参考时钟发生器。
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公开(公告)号：US20140226166A1
公开(公告)日：2014-08-14
申请号：US14343932
申请日：2012-09-10
IPC分类号： G01B11/24
CPC分类号： H03M1/002 , G01B11/24 , G01T1/1647 , G04F10/005 , H04N5/378 , H04N13/20 , H04N2213/001
摘要： 3D imager including at least one pixel, each pixel including a photodetector for detecting photon incidence and a time-to-digital converter system configured for referencing the photon incidence to a reference clock, and further including a reference clock generator provided for generating the reference clock, wherein the reference clock generator is configured for adjusting the frequency of the reference clock on the basis of an estimated time up to a subsequent photon incidence.
摘要翻译： 3D成像器包括至少一个像素，每个像素包括用于检测光子入射的光电检测器和配置用于参考光子入射到参考时钟的时间数字转换器系统，并且还包括参考时钟发生器，用于产生参考时钟 ，其中所述参考时钟发生器被配置为基于直到随后的光子入射的估计时间来调整所述参考时钟的频率。
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公开(公告)号：US20060290435A1
公开(公告)日：2006-12-28
申请号：US11464420
申请日：2006-08-14
IPC分类号： H03L7/00
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。
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6.发明申请FAST HOPPING FREQUENCY SYNTHESIZER USING AN ALL DIGITAL PHASED LOCKED LOOP (ADPLL) 有权使用所有数字相位锁定环路（ADPLL）快速搜寻频率合成器公开(公告)号：US20060256910A1
公开(公告)日：2006-11-16
申请号：US11382570
申请日：2006-05-10
申请人： Nir Tal , Robert Staszewski , Ofer Friedman
发明人： Nir Tal , Robert Staszewski , Ofer Friedman
CPC分类号： H04B1/7136 , H03C3/40 , H03D3/007 , H03L7/08 , H03L7/0991 , H04B1/71635 , H04B1/71637 , H04B2001/71365
摘要： A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/fT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency. A mixer applies the waveform to the I and Q data samples prior to conversion to the digital domain.
摘要翻译： 一种新颖有用的快速频率合成器和发射机。 频率合成器和发射器包含适用于操作开环的数字控制振荡器（DCO）。 通过改变振荡器调谐字（OTW）来模拟UWB发射机的三个振荡器来实现瞬时频率切换。 在一个实施例中，DCO可以在用于构造DCO的变容二极管装置的1 / f T T中瞬时改变频率。 在数据包发送或接收开始之前，全数字锁相环（ADPLL）用于离线校准。 开关期间的任何相移都由发射机中的数字电路跟踪。 在第二实施例中，通过使用有效地产生有效地移动合成频率的精细分辨率复指数波形的数控振荡器（NCO）来提供额外的频率精度。 混频器在转换为数字域之前将波形应用于I和Q数据采样。
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公开(公告)号：US20050287967A1
公开(公告)日：2005-12-29
申请号：US11115815
申请日：2005-04-26
CPC分类号： H04B1/0483 , H03F1/3241 , H03F1/3294 , H03F3/191 , H03F2200/331
摘要： A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.
摘要翻译： 一种低噪声，高隔离，全数字发送缓冲增益控制机制的新型设备。 增益控制方案在全数字直接数/频幅度转换器（DRAC）的上下文中呈现，该转换器有效地结合了上变频，I和Q组合，D / A转换，滤波，缓冲和 RF输出幅度控制成单个电路。 发送缓冲器构造为NMOS开关阵列。 每个NMOS开关的控制逻辑包括一个通门型AND门，其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。 通过在CMOS工艺中实现时，通过识别伪E类预功率放大器（PPA）所遭受的损伤来实现功率控制。 首先，阵列的NMOS开关具有大的导通电阻，因此当输入波形为高时，只能从RF扼流圈画出有限的电流。 在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制，并允许控制RF输出功率的全数字方法。
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8.发明申请Wireless communications device having type-II all-digital phase-locked loop (PLL) 有权具有II型全数字锁相环（PLL）的无线通信设备公开(公告)号：US20050212606A1
公开(公告)日：2005-09-29
申请号：US11122670
申请日：2005-05-04
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。
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公开(公告)号：US20050130618A1
公开(公告)日：2005-06-16
申请号：US11028995
申请日：2005-01-03
申请人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译： 具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。 然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。 提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。 利用混频器中不同采样电容器之间的显着电容差和叠加特性。
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公开(公告)号：US20050025270A1
公开(公告)日：2005-02-03
申请号：US10924303
申请日：2004-08-23
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
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