公开(公告)号：US12230347B2

公开(公告)日：2025-02-18

申请号：US18322997

申请日：2023-05-24

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US20230298682A1

公开(公告)日：2023-09-21

申请号：US18322997

申请日：2023-05-24

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/18

CPC classification number: G11C29/42 ,  G11C29/44 ,  G11C7/1045 ,  G11C29/18 ,  G11C2029/1202

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US11372717B2

公开(公告)日：2022-06-28

申请号：US16944110

申请日：2020-07-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Michael Hawjing Lo ,  Dexter Tamio Chun ,  Xavier Loic Leloup ,  Laurent Rene Moll

IPC: G06F11/10 ,  G06F3/06

Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

公开(公告)号：US11295803B2

公开(公告)日：2022-04-05

申请号：US16945303

申请日：2020-07-31

Applicant: QUALCOMM Incorporated ,  Candace Sachi Chun

Inventor： Jungwon Suh ,  Michael Hawjing Lo ,  Dexter Tamio Chun ,  Xavier Loic Leloup ,  Laurent Rene Moll

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/409

Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.

公开(公告)号：US20210358559A1

公开(公告)日：2021-11-18

申请号：US17245981

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C7/10

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US11728003B2

公开(公告)日：2023-08-15

申请号：US17245981

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/18 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C7/1045 ,  G11C29/18 ,  G11C29/44 ,  G11C2029/1202

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US11520706B2

公开(公告)日：2022-12-06

申请号：US17244398

申请日：2021-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Alain Artieri ,  Rakesh Kumar Gupta ,  Subbarao Palacharla ,  Kedar Bhole ,  Laurent Rene Moll ,  Carlo Spitale ,  Sparsh Singhai ,  Shyamkumar Thoziyoor ,  Gopi Tummala ,  Christophe Avoinne ,  Samir Ginde ,  Syed Minhaj Hassan ,  Jean-Jacques Lecler ,  Luigi Vinci

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/12

Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.