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公开(公告)号：US10853163B2
公开(公告)日：2020-12-01
申请号：US15942372
申请日：2018-03-30
Applicant: QUALCOMM Incorporated
Inventor： Alain Artieri , Deepti Vijayalakshmi Sriramagiri , Dexter Tamio Chun , Jungwon Suh
Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.
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公开(公告)号：US10387242B2
公开(公告)日：2019-08-20
申请号：US15682533
申请日：2017-08-21
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Alain Artieri , Dexter Tamio Chun , Deepti Vijayalakshmi Sriramagiri
Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.
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公开(公告)号：US10180908B2
公开(公告)日：2019-01-15
申请号：US14710693
申请日：2015-05-13
Applicant: QUALCOMM Incorporated
Inventor： Yanru Li , Subbarao Palacharla , Moinul Khan , Alain Artieri , Azzedine Touzni
IPC: G06F12/08 , G06F12/10 , G06F12/0888 , G06F12/084 , G06F12/0893 , G06F12/0895 , G06F12/1045
Abstract: Aspects include computing devices, systems, and methods for implementing a cache maintenance or status operation for a component cache of a system cache. A computing device may generate a component cache configuration table, assign at least one component cache indicator of a component cache to a master of the component cache, and map at least one control register to the component cache indicator by a centralized control entity. The computing device may store the component cache indicator such that the component cache indicator is accessible by the master of the component cache for discovering a virtualized view of the system cache and issuing a cache maintenance or status command for the component cache bypassing the centralized control entity. The computing device may receive the cache maintenance or status command by a control register associated with a cache maintenance or status command and the component cache bypassing the centralized control entity.
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公开(公告)号：US20180284878A1
公开(公告)日：2018-10-04
申请号：US15471865
申请日：2017-03-28
Applicant: QUALCOMM Incorporated
Inventor： Alain Artieri , Jean-Marie Tran
CPC classification number: G06F1/3296 , G06F1/189 , G06F1/324 , H03K5/1565 , Y02D10/126 , Y02D10/172
Abstract: An integrated circuit (IC) is disclosed herein for power management using duty cycles. In an example aspect, the integrated circuit includes multiple power domains, each of which includes a respective power state controller. The power state controller acts as a bridge between global supply lines of the integrated circuit and local supply lines of the respective power domain. Global supply lines can include a first global power rail, a second global power rail, and a global clock tree. Local supply lines can include a local power rail and a local clock tree. In operation, a power state controller adjusts a power state of the respective power domain in accordance with a duty cycle. A timeslot corresponding to the duty cycle can be separated into multiple time periods with durations of the time periods being based on the duty cycle.
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公开(公告)号：US10089238B2
公开(公告)日：2018-10-02
申请号：US14334010
申请日：2014-07-17
Applicant: QUALCOMM Incorporated
Inventor： Subbarao Palacharla , Moinul Khan , Alain Artieri , Kedar Bhole , Vinod Chamarty , Yanru Li , Raghu Sankuratri , George Patsilaras , Pavan Kumar Thirunagari , Andrew Edmund Turner , Jeong-Ho Woo
IPC: G06F12/00 , G06F12/0893 , G06F12/084 , G06F12/0895 , G06F9/50 , G06F12/0888 , G06F12/0864 , G06F1/32 , G06F17/30
Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.
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Patent Agency Ranking
公开(公告)号：US09785371B1
公开(公告)日：2017-10-10
申请号：US15081915
申请日：2016-03-27
Applicant: QUALCOMM INCORPORATED
Inventor： Yanru Li , Dexter Tamio Chun , Alain Artieri
IPC: G06F1/32 , G06F3/06 , G06F12/0862 , G11C11/406
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0611 , G06F3/0653 , G06F3/0685 , G06F12/0862 , G06F2212/1021 , G06F2212/1024 , G06F2212/222 , G06F2212/602 , G11C11/40607 , Y02D10/13
Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem adjusts access to the DRAM based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.
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公开(公告)号：US09778871B1
公开(公告)日：2017-10-03
申请号：US15081914
申请日：2016-03-27
Applicant: QUALCOMM INCORPORATED
Inventor： Yanru Li , Dexter Tamio Chun , Alain Artieri
IPC: G06F1/32 , G06F3/06 , G06F12/0862 , G11C11/406 , G11C7/10
CPC classification number: G06F1/3296 , G06F1/324 , G06F1/3275 , G06F12/0862 , G06F13/1689 , G06F2212/1021 , G06F2212/1024 , G06F2212/222 , G06F2212/602 , G11C11/40607 , G11C2211/4067 , Y02D10/14
Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.
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公开(公告)号：US20240402944A1
公开(公告)日：2024-12-05
申请号：US18495215
申请日：2023-10-26
Applicant: QUALCOMM Incorporated
Inventor： Alain Artieri , Jungwon Suh , Subbarao Palacharla , Vikrant Kumar , Riccardo Iacobacci
IPC: G06F3/06
Abstract: This disclosure provides systems, methods, and devices for memory systems that support processing data and metadata within a memory of a memory device. In a first aspect, a method of controlling a memory device includes executing a first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion; and executing a second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank. Other aspects and features are also claimed and described.
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公开(公告)号：US11281526B2
公开(公告)日：2022-03-22
申请号：US17008442
申请日：2020-08-31
Applicant: QUALCOMM Incorporated
Inventor： Alain Artieri , Deepti Vijayalakshmi Sriramagiri , Dexter Tamio Chun , Jungwon Suh
Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.
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公开(公告)号：US10922168B2
公开(公告)日：2021-02-16
申请号：US16503368
申请日：2019-07-03
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Alain Artieri , Dexter Tamio Chun , Deepti Vijayalakshmi Sriramagiri
Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.
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