公开(公告)号：US09612970B2

公开(公告)日：2017-04-04

申请号：US14333981

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Pankaj Chaurasia ,  Raghu Sankuratri

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/084 ,  G06F12/12 ,  G06F12/10 ,  G06F12/0895

CPC classification number: G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

公开(公告)号：US09734070B2

公开(公告)日：2017-08-15

申请号：US14921468

申请日：2015-10-23

Applicant: QUALCOMM INCORPORATED

Inventor： Alain Artieri ,  Subbarao Palacharla ,  Laurent Moll ,  Raghu Sankuratri ,  Kedar Bhole ,  Vinod Chamarty

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/127 ,  G06F12/0864 ,  G06F12/123

CPC classification number: G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/601 ,  G06F2212/62

Abstract: A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.

公开(公告)号：US20160019157A1

公开(公告)日：2016-01-21

申请号：US14333981

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Pankaj Chaurasia ,  Raghu Sankuratri

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

Abstract translation: 方面包括计算设备，系统和用于通过集合和方式将系统高速缓存分组到组件高速缓存中的方法。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收指定组件高速缓存标识符的系统高速缓存访​​问请求，并且将组件高速缓存标识符与组件高速缓存标识符的特征与组件高速缓存配置表相关联的记录进行匹配。 组件缓存特征可以包括设置的移动特征，设置偏移特征和目标方式，其可以定义系统高速缓存中的组件高速缓存的位置。 系统高速缓冲存储器控制器还可以在系统高速缓存访​​问请求中接收系统高速缓存的物理地址，确定组件高速缓存的索引模式，并转换组件高速缓存的物理地址。

公开(公告)号：US20230029696A1

公开(公告)日：2023-02-02

申请号：US17390274

申请日：2021-07-30

Applicant: QUALCOMM Incorporated

Inventor： Girish Bhat ,  Subbarao Palacharla ,  Jeffrey Shabel ,  Isaac Berk ,  Kedar Bhole ,  Vipul Gandhi ,  George Patsilaras ,  Sparsh Singhai

IPC: G06F12/084 ,  G06F1/3212

Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

公开(公告)号：US10089238B2

公开(公告)日：2018-10-02

申请号：US14334010

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Yanru Li ,  Raghu Sankuratri ,  George Patsilaras ,  Pavan Kumar Thirunagari ,  Andrew Edmund Turner ,  Jeong-Ho Woo

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F9/50 ,  G06F12/0888 ,  G06F12/0864 ,  G06F1/32 ,  G06F17/30

Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

公开(公告)号：US11803472B2

公开(公告)日：2023-10-31

申请号：US17390274

申请日：2021-07-30

Applicant: QUALCOMM Incorporated

Inventor： Girish Bhat ,  Subbarao Palacharla ,  Jeffrey Shabel ,  Isaac Berk ,  Kedar Bhole ,  Vipul Gandhi ,  George Patsilaras ,  Sparsh Singhai

IPC: G06F12/084 ,  G06F1/3212

CPC classification number: G06F12/084 ,  G06F1/3212 ,  G06F2212/62

Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

公开(公告)号：US11520706B2

公开(公告)日：2022-12-06

申请号：US17244398

申请日：2021-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Alain Artieri ,  Rakesh Kumar Gupta ,  Subbarao Palacharla ,  Kedar Bhole ,  Laurent Rene Moll ,  Carlo Spitale ,  Sparsh Singhai ,  Shyamkumar Thoziyoor ,  Gopi Tummala ,  Christophe Avoinne ,  Samir Ginde ,  Syed Minhaj Hassan ,  Jean-Jacques Lecler ,  Luigi Vinci

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/12

Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.

公开(公告)号：US20160019158A1

公开(公告)日：2016-01-21

申请号：US14334010

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Yanru Li ,  Raghu Sankuratri ,  George Patsilaras ,  Pavan Kumar Thirunagari ,  Andrew Edward Turner ,  Jeong-Ho Woo

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0888 ,  G06F12/0895 ,  G06F17/30902 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6042 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

Abstract translation: 方面包括计算设备，系统和方法，用于通过集合和方式动态地将系统高速缓存分区到组件高速缓存中。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收系统高速缓存访​​问请求，并且在系统高速缓存中保留对应于与请求的组件高速缓存标识符相关联的组件高速缓存的位 在系统缓存中预留位置可以激活系统高速缓存中的位置以供请求客户端使用，并且还可以防止其他客户端使用系统高速缓存中的保留位置。 释放系统缓存中的位置可以停用系统缓存中的位置，并允许其他客户端使用它们。 保留系统缓存中的位置的客户端可以改变其在其组件高速缓存中保留的位置的数量。