公开(公告)号：US12038855B2

公开(公告)日：2024-07-16

申请号：US17650455

申请日：2022-02-09

Applicant: QUALCOMM Incorporated

Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

公开(公告)号：US09489305B2

公开(公告)日：2016-11-08

申请号：US14571876

申请日：2014-12-16

Applicant: QUALCOMM INCORPORATED

Inventor： George Patsilaras ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  Kris Tiri ,  Jeong-Ho Woo ,  Anwar Rohillah ,  Feng Wang ,  Moinul Khan ,  Subbarao Palacharla

IPC: G06F12/00 ,  G06F12/08 ,  G06F1/32 ,  G06F13/16 ,  G06F9/46

CPC classification number: G06F12/0802 ,  G06F1/3253 ,  G06F9/467 ,  G06F12/0804 ,  G06F12/0835 ,  G06F12/0891 ,  G06F13/16 ,  G06F2212/604 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

Abstract translation: 公开了用于在芯片上的系统（“SoC”）中管理从主组件到长期存储器组件的写事务量的方法和系统的各种实施例。 因为当临时数据从紧密耦合的存储器组件（例如低级缓存“LLC”存储器））写入长期存储器（例如双倍数据速率“DDR”存储器）时，功耗和总线带宽被不必要地消耗 数据生成主组件，解决方案的实施例寻求识别包含短暂数据的写事务，并防止短暂数据被写入DDR。

公开(公告)号：US20250068574A1

公开(公告)日：2025-02-27

申请号：US18454658

申请日：2023-08-23

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Pankaj Deshmukh ,  Subbarao Palacharla ,  Alain Artieri

IPC: G06F13/16 ,  G06F1/3234 ,  G06F13/28

Abstract: This disclosure provides systems, methods, and devices for memory systems that support an efficient mode for reducing power consumption in a memory module while maintaining access to all contents of memory. In a first aspect, a method includes communicating, by a memory module, first data stored in a first plurality of banks to a host device through a first sub-channel in a first operating mode; communicating second data stored in the second plurality of banks to the host device through a second sub-channel in the first operating mode; receiving a command to enter a second operating mode; and communicating third data stored in the first plurality of banks and fourth data stored in the second plurality of banks to the host device through the first sub-channel in the second operating mode. Other aspects and features are also claimed and described.

公开(公告)号：US12159033B2

公开(公告)日：2024-12-03

申请号：US18047493

申请日：2022-10-18

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Pankaj Deshmukh ,  Michael Hawjing Lo ,  Subbarao Palacharla ,  Olivier Alavoine

IPC: G06F3/06

Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.

公开(公告)号：US20230305971A1

公开(公告)日：2023-09-28

申请号：US17650455

申请日：2022-02-09

Applicant: QUALCOMM Incorporated

Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

公开(公告)号：US09734070B2

公开(公告)日：2017-08-15

申请号：US14921468

申请日：2015-10-23

Applicant: QUALCOMM INCORPORATED

Inventor： Alain Artieri ,  Subbarao Palacharla ,  Laurent Moll ,  Raghu Sankuratri ,  Kedar Bhole ,  Vinod Chamarty

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/127 ,  G06F12/0864 ,  G06F12/123

CPC classification number: G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/601 ,  G06F2212/62

Abstract: A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.

公开(公告)号：US20160335190A1

公开(公告)日：2016-11-17

申请号：US14710693

申请日：2015-05-13

Applicant: QUALCOMM Incorporated

Inventor： Yanru Li ,  Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Azzedine Touzni

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0888 ,  G06F12/084 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/1045 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/608 ,  G06F2212/65 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache maintenance or status operation for a component cache of a system cache. A computing device may generate a component cache configuration table, assign at least one component cache indicator of a component cache to a master of the component cache, and map at least one control register to the component cache indicator by a centralized control entity. The computing device may store the component cache indicator such that the component cache indicator is accessible by the master of the component cache for discovering a virtualized view of the system cache and issuing a cache maintenance or status command for the component cache bypassing the centralized control entity. The computing device may receive the cache maintenance or status command by a control register associated with a cache maintenance or status command and the component cache bypassing the centralized control entity.

Abstract translation: 方面包括用于实现系统高速缓存的组件高速缓存的高速缓存维护或状态操作的计算设备，系统和方法。 计算设备可以生成组件高速缓存配置表，将组件高速缓存的至少一个组件高速缓存指示符分配给组件高速缓存的主设备，并且通过集中控制实体将至少一个控制寄存器映射到组件高速缓存指示器。 计算设备可以存储组件高速缓存指示符，使得组件高速缓存指示符可被组件高速缓存的主机访问，用于发现系统高速缓存的虚拟化视图，并且发出用于绕过集中控制实体的组件高速缓存的高速缓存维护或状态命令 。 计算设备可以通过与高速缓存维护或状态命令相关联的控制寄存器以及绕过集中控制实体的组件高速缓存来接收高速缓存维护或状态命令。

公开(公告)号：US20160019157A1

公开(公告)日：2016-01-21

申请号：US14333981

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Pankaj Chaurasia ,  Raghu Sankuratri

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

Abstract translation: 方面包括计算设备，系统和用于通过集合和方式将系统高速缓存分组到组件高速缓存中的方法。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收指定组件高速缓存标识符的系统高速缓存访​​问请求，并且将组件高速缓存标识符与组件高速缓存标识符的特征与组件高速缓存配置表相关联的记录进行匹配。 组件缓存特征可以包括设置的移动特征，设置偏移特征和目标方式，其可以定义系统高速缓存中的组件高速缓存的位置。 系统高速缓冲存储器控制器还可以在系统高速缓存访​​问请求中接收系统高速缓存的物理地址，确定组件高速缓存的索引模式，并转换组件高速缓存的物理地址。

公开(公告)号：US20240402944A1

公开(公告)日：2024-12-05

申请号：US18495215

申请日：2023-10-26

Applicant: QUALCOMM Incorporated

Inventor： Alain Artieri ,  Jungwon Suh ,  Subbarao Palacharla ,  Vikrant Kumar ,  Riccardo Iacobacci

IPC: G06F3/06

Abstract: This disclosure provides systems, methods, and devices for memory systems that support processing data and metadata within a memory of a memory device. In a first aspect, a method of controlling a memory device includes executing a first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion; and executing a second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank. Other aspects and features are also claimed and described.

公开(公告)号：US20240311317A1

公开(公告)日：2024-09-19

申请号：US18674138

申请日：2024-05-24

Applicant: QUALCOMM Incorporated

Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.