Abstract:
Amplifiers with noise splitting to improve noise figure are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes a plurality of amplifier circuits and at least one interconnection circuit. The amplifier circuits receive an input radio frequency (RF) signal. The interconnection circuit(s) are coupled between the plurality of amplifier circuits. Each interconnection circuit is closed to short the outputs or internal nodes of two amplifier circuits coupled to that interconnection circuit. The plurality of amplifier circuits may include a plurality of gain circuits coupled to a plurality of current buffers, one gain circuit and one current buffer for each amplifier circuit. Each amplifier circuit provides an output current, which may include a portion of the current from each of the plurality of gain circuits when the plurality of amplifier circuits are enabled.
Abstract:
An apparatus includes a first amplifier circuit and a second amplifier circuit. The first amplifier circuit has a first output coupled to a first load circuit in a multi-output mode, and the second amplifier circuit has a second output coupled to a second load circuit in the multi-output mode. The apparatus further includes a first divert circuit and a second divert circuit. The first divert circuit is configured to divert a first portion of a first amplified signal from the first amplifier circuit to the second load circuit in the multi-output mode. The second divert circuit is configured to divert a first portion of a second amplified signal from the second amplifier circuit to the first load circuit in the multi-output mode.
Abstract:
Amplifiers with noise splitting to improve noise figure are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes a plurality of amplifier circuits and at least one interconnection circuit. The amplifier circuits receive an input radio frequency (RF) signal. The interconnection circuit(s) are coupled between the plurality of amplifier circuits. Each interconnection circuit is closed to short the outputs or internal nodes of two amplifier circuits coupled to that interconnection circuit. The plurality of amplifier circuits may include a plurality of gain circuits coupled to a plurality of current buffers, one gain circuit and one current buffer for each amplifier circuit. Each amplifier circuit provides an output current, which may include a portion of the current from each of the plurality of gain circuits when the plurality of amplifier circuits are enabled.
Abstract:
Techniques for improving electro-static discharge (ESD) performance in integrated circuits (IC's). In an aspect, one or more protective diodes are provided between various nodes of the IC. For example, protective diode(s) may be provided between the drain and gate of an amplifier input transistor, and/or between the drain and ground, etc. In certain exemplary embodiments, the amplifier may be a cascode amplifier. Further aspects for effectively dealing with ESD phenomena are described.
Abstract:
A CMOS amplifier including electrostatic discharge (ESD) protection circuits is disclosed. In one embodiment, the CMOS amplifier may include a PMOS transistor, a NMOS transistor, primary protection diodes, and one or more auxiliary protection diodes to limit a voltage difference between terminals of the CMOS amplifier. In some embodiments, the auxiliary protection diodes may limit the voltage difference between an input terminal of the CMOS amplifier and a supply voltage, the input terminal of the CMOS amplifier and ground, and the input terminal and the output terminal of the CMOS amplifier.
Abstract:
A CMOS amplifier including electrostatic discharge (ESD) protection circuits is disclosed. In one embodiment, the CMOS amplifier may include a PMOS transistor, a NMOS transistor, primary protection diodes, and one or more auxiliary protection diodes to limit a voltage difference between terminals of the CMOS amplifier. In some embodiments, the auxiliary protection diodes may limit the voltage difference between an input terminal of the CMOS amplifier and a supply voltage, the input terminal of the CMOS amplifier and ground, and the input terminal and the output terminal of the CMOS amplifier.
Abstract:
An apparatus includes a first amplifier circuit and a second amplifier circuit. The first amplifier circuit has a first output coupled to a first load circuit in a multi-output mode, and the second amplifier circuit has a second output coupled to a second load circuit in the multi-output mode. The apparatus further includes a first divert circuit and a second divert circuit. The first divert circuit is configured to divert a first portion of a first amplified signal from the first amplifier circuit to the second load circuit in the multi-output mode. The second divert circuit is configured to divert a first portion of a second amplified signal from the second amplifier circuit to the first load circuit in the multi-output mode.
Abstract:
Multi-output amplifiers with configurable source degeneration inductance and having good performance are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) includes a gain transistor and a configurable degeneration inductor for an amplifier. The gain transistor receives an input signal and provides an amplified signal. The amplifier provides a single output signal in a first operating mode or a plurality of output signals in a second operating mode. The configurable degeneration inductor is coupled to the gain transistor and provides a first source degeneration inductance in the first operating mode or a second source degeneration inductance in the second operating mode. The second source degeneration inductance is less than the first source degeneration inductance and may be dependent on the number of output signals generated in the second operating mode.
Abstract:
Techniques for improving electro-static discharge (ESD) performance in integrated circuits (IC's). In an aspect, one or more protective diodes are provided between various nodes of the IC. For example, protective diode(s) may be provided between the drain and gate of an amplifier input transistor, and/or between the drain and ground, etc. In certain exemplary embodiments, the amplifier may be a cascode amplifier. Further aspects for effectively dealing with ESD phenomena are described.
Abstract:
Amplifiers with multiple outputs and separate gain control per output are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) may include first and second amplifier circuits. The first amplifier circuit may receive and amplify an input radio frequency (RF) signal based on a first variable gain and provide a first amplified RF signal. The second amplifier circuit may receive and amplify the input RF signal based on a second variable gain and provide a second amplified RF signal. The input RF signal may include a plurality of transmitted signals being received by the wireless device. The first variable gain may be adjustable independently of the second variable gain. Each variable gain may be set based on the received power level of at least one transmitted signal being received by the wireless device.