公开(公告)号：US20170371990A1

公开(公告)日：2017-12-28

申请号：US15192278

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Magnus Olov WIKLUND ,  Emanuele LOPELLI ,  Charles WANG

IPC: G06F17/50 ,  H04W88/02 ,  H03L7/093 ,  H03L7/099

CPC classification number: G06F17/5036 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03C3/0991 ,  H03L7/093 ,  H03L7/0991 ,  H03L2207/12 ,  H03L2207/50 ,  H04W88/02

Abstract: A method of calibrating an All-Digital Phase Locked Loop (ADPLL) includes obtaining a model of the ADPLL and applying an input signal to both the ADPLL and to the model. The ADPLL generates an actual output of the ADPLL, while the model generates a model output. An error between the actual output of the ADPLL and the model output is then sensed. The method also includes generating a calibration value based on the error between the actual output of the ADPLL and the model output, and adjusting a feedforward gain of the ADPLL based on the calibration value.

公开(公告)号：US20170134030A1

公开(公告)日：2017-05-11

申请号：US15163480

申请日：2016-05-24

Applicant: QUALCOMM Incorporated

Inventor： Mahbod MOFIDI ,  Emanuele LOPELLI ,  Magnus Olov WIKLUND ,  Charles WANG

IPC: H03L7/10 ,  H03L7/099 ,  H03L7/197 ,  H03L7/113 ,  H03L7/091 ,  H03B5/32 ,  H03B1/04

CPC classification number: H03L7/104 ,  H03L7/04 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/113 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03L2207/50

Abstract: Disclosed are methods and apparatuses for reducing fractional spurs in an All-Digital Phase Lock Loop (ADPLL). An exemplary apparatus includes a crystal oscillator configured to generate a first frequency reference signal, a non-integer divider coupled to the crystal oscillator and configured to divide the first frequency reference signal by a non-integer variable to generate a second frequency reference signal, and a multiplexor coupled to the non-integer divider and the crystal oscillator and configured to output the first frequency reference signal or the second frequency reference signal to the ADPLL, wherein the multiplexor is configured to output the second frequency reference signal based on the ADPLL being tuned to a low fractionality channel.