公开(公告)号：US11605594B2

公开(公告)日：2023-03-14

申请号：US17017361

申请日：2020-09-10

Applicant: QUALCOMM Incorporated

Inventor： Ryan Lane ,  Li-Sheng Weng ,  Charles David Paynter ,  Eric David Foronda

IPC: H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: A package comprising a substrate, an integrated device, and an interconnect integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnect integrated device is coupled to a surface of the substrate. The integrated device, the interconnect integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, that travels through at least the substrate, then through the interconnect integrated device and back through the substrate.

公开(公告)号：US11784157B2

公开(公告)日：2023-10-10

申请号：US17339830

申请日：2021-06-04

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng Weng ,  Charles David Paynter ,  Ryan Lane ,  Jianwen Xu ,  William Stone

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L24/73 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/20 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17163 ,  H01L2224/2105 ,  H01L2224/24145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

公开(公告)号：US20240107665A1

公开(公告)日：2024-03-28

申请号：US17934651

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Biancun Xie ,  Shree Krishna Pandey ,  Chin-Kwan Kim ,  Ryan Lane ,  Charles David Paynter

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K3/4644 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/10015 ,  H05K2201/10734

Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

公开(公告)号：US12160952B2

公开(公告)日：2024-12-03

申请号：US17934651

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Biancun Xie ,  Shree Krishna Pandey ,  Chin-Kwan Kim ,  Ryan Lane ,  Charles David Paynter

IPC: H05K1/00 ,  H05K1/02 ,  H05K3/46

Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

公开(公告)号：US20240371736A1

公开(公告)日：2024-11-07

申请号：US18310331

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Omar James Bchir ,  Dongming He ,  Ryan Lane ,  Kuiwon Kang ,  Lily Zhao

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

Abstract: Substrate employing core with cavity embedding reduced height electrical device(s), and related integrated circuit (IC) packages and fabrication methods are also disclosed. The cavity of the core (that has one or more core layers) of the substrate includes an embedded electrical device structure that an electrical device built upon another second component(s) to make the overall height of the electrical device structure compatible with the height of the cavity of the core. In this manner, the design criteria used to select thickness or height of the core for providing the desired stability in the substrate can be incompatible with the thickness or the height of the embedded electrical device.

公开(公告)号：US11452246B2

公开(公告)日：2022-09-20

申请号：US17071408

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Charles David Paynter ,  Ryan Lane ,  John Eaton ,  Amit Mano

IPC: H05K9/00 ,  H05K1/02 ,  H05K3/30 ,  H05K5/00 ,  H05K1/11

Abstract: A device that includes a board, a package and a patch substrate. The board includes a cavity. The package is coupled to a first side of the board. The package includes a substrate and an integrated device coupled to the substrate. The integrated device is located at least partially in the cavity of the board. The patch substrate is coupled to a second side of the board. The patch substrate is located over the cavity of the board. The patch substrate is configured as an electromagnetic interference (EMI) shield for the package.