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Patent Agency Ranking
公开(公告)号：US09430407B2
公开(公告)日：2016-08-30
申请号：US14530261
申请日：2014-10-31
Applicant: QUALCOMM Incorporated
Inventor： Jian Shen , Lew Go Chua-Eoan
CPC classification number: G06F12/1416 , G06F3/0622 , G06F3/0653 , G06F3/0673 , G06F9/4418 , G06F11/0727 , G06F11/0766 , G06F2212/1052
Abstract: A machine state vector is received at a memory. The machine state vector has a machine state and a machine identifier. Write access qualification is met if the machine state entry is an initial write, or if the machine identifier matches the machine identifier of a stored machine state vector, and machine identifier and machine state are stored in the memory. A fetch machine state request is received, having a requestor machine identifier. A machine state retrieval qualification is met by the requestor machine identifier matching the stored machine identifier, and the machine state is retrieved.
Abstract translation: 在存储器处接收机器状态向量。 机器状态向量具有机器状态和机器标识符。 如果机器状态条目是初始写入，或者机器标识符与存储的机器状态向量的机器标识符相匹配，并且机器标识符和机器状态存储在存储器中，则满足写访问限定条件。 接收到获取机器状态请求，具有请求者机器标识符。 通过与存储的机器标识符匹配的请求者机器标识符来满足机器状态检索限定条件，并检索机器状态。
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公开(公告)号：US09349692B2
公开(公告)日：2016-05-24
申请号：US14703240
申请日：2015-05-04
Applicant: QUALCOMM Incorporated
Inventor： Yuan-cheng Christopher Pan , Fifin Sweeney , Lew Go Chua-Eoan , Zhi Zhu , Junmou Zhang , Jason Gonzalez
IPC: H05K7/00 , H01L23/538 , H01L23/00 , H01L25/065 , H05K1/18 , H05K1/11 , H05K1/16
CPC classification number: H01L23/5384 , H01L23/49822 , H01L23/642 , H01L23/645 , H01L24/02 , H01L24/16 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L2224/02371 , H01L2224/05624 , H01L2224/13025 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/48227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06544 , H01L2924/00014 , H01L2924/1205 , H01L2924/1206 , H01L2924/14 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H05K1/11 , H05K1/165 , H05K1/181 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.
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公开(公告)号：US09411745B2
公开(公告)日：2016-08-09
申请号：US14046341
申请日：2013-10-04
Applicant: QUALCOMM Incorporated
Inventor： Jian Shen , Lew Go Chua-Eoan
IPC: G06F12/10
CPC classification number: G06F12/1027 , G06F12/1009 , G06F12/1036 , G06F2212/656 , G06F2212/683
Abstract: Methods, devices, and instructions for performing a reverse translation lookaside buffer (TLB) look-up using a physical address input, including obtaining with a first processor the physical address input, wherein the physical address input indicates a physical address corresponding to a shared memory, obtaining a first mask associated with a first virtual address from a first TLB entry within a TLB associated with the first processor, wherein the obtained first mask is a bit pattern, obtaining from the first TLB entry a first page frame number associated with the shared memory, applying the obtained first mask to the obtained first page frame number to generate a first value, applying the obtained first mask to the obtained physical address input to generate a second value, and comparing the first value and the second value to determine whether the first value and the second value match.
Abstract translation: 用于使用物理地址输入来执行反向翻译后备缓冲器（TLB）查找的方法，设备和指令，包括用第一处理器获取物理地址输入，其中物理地址输入指示对应于共享存储器的物理地址 从与所述第一处理器相关联的TLB内的第一TLB条目获得与第一虚拟地址相关联的第一掩码，其中所获得的第一掩码是位模式，从所述第一TLB条目获得与所述共享 存储器，将所获得的第一掩模应用于获得的第一页帧号以产生第一值，将获得的第一掩码应用于获得的物理地址输入以产生第二值，并且比较第一值和第二值以确定是否 第一个值和第二个值匹配。
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公开(公告)号：US09613675B2
公开(公告)日：2017-04-04
申请号：US14106730
申请日：2013-12-14
Applicant: QUALCOMM Incorporated
Inventor： Jian Shen , Lew Go Chua-Eoan
CPC classification number: G11C11/1675 , G11C7/1009 , G11C7/109 , G11C7/12 , G11C11/1673 , G11C2207/2263
Abstract: A method includes performing a memory operation at a magnetic tunnel junction (MTJ) storage element by, during a single memory clock cycle, reading a first value stored at the MTJ storage element, comparing the first value to a second value to be stored at the MTJ storage element, and selectively writing the second value to the MTJ storage element based on the comparison.
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公开(公告)号：US20150170727A1
公开(公告)日：2015-06-18
申请号：US14106730
申请日：2013-12-14
Applicant: QUALCOMM Incorporated
Inventor： Jian Shen , Lew Go Chua-Eoan
IPC: G11C11/16
CPC classification number: G11C11/1675 , G11C7/1009 , G11C7/109 , G11C7/12 , G11C11/1673 , G11C2207/2263
Abstract: A method includes performing a memory operation at a magnetic tunnel junction (MTJ) storage element by, during a single memory clock cycle, reading a first value stored at the MTJ storage element, comparing the first value to a second value to be stored at the MTJ storage element, and selectively writing the second value to the MTJ storage element based on the comparison.
Abstract translation: 一种方法包括：在单个存储器时钟周期期间，在磁性隧道结（MTJ）存储元件处执行存储器操作，读取存储在MTJ存储元件中的第一值，将第一值与要存储在第二值 MTJ存储元件，并且基于该比较选择性地将第二值写入MTJ存储元件。
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