-
1.发明申请CIRCUITS AND METHODS PROVIDING STATE INFORMATION PRESERVATION DURING POWER SAVING OPERATIONS 有权节电操作期间提供状态信息保存的电路和方法公开(公告)号：US20160246356A1
公开(公告)日：2016-08-25
申请号：US14630392
申请日：2015-02-24
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3243 , G06F1/3265 , G06F1/3293 , G06F1/3296 , Y02D10/152 , Y02D10/171
摘要： Methods, systems, and circuits for preserving state information during power saving operations are disclosed. One example embodiment includes a circuit having a processing core, where the processing core includes logic processing circuits as well as circuits (e.g., flip-flops registers) that are used to store state information in the processing core. The logic processing circuits have power connections to a power rail that are subject to a switch, which can disconnect the power connections from the power rail. The circuits that are used to store state information have different power connections that are subject to a different switch. Therefore, the logic processing circuits and the state information circuits can be separately power-collapsed.
摘要翻译： 公开了用于在省电操作期间保持状态信息的方法，系统和电路。 一个示例实施例包括具有处理核心的电路，其中处理核心包括逻辑处理电路以及用于在处理核心中存储状态信息的电路（例如，触发器寄存器）。 逻辑处理电路具有经受切换的电力轨的电力连接，这可以将电力连接从电力轨道断开。 用于存储状态信息的电路具有不同的电源连接，这些电源连接受不同的开关的影响。 因此，逻辑处理电路和状态信息电路可以单独断电。
-
公开(公告)号：US10528117B2
公开(公告)日：2020-01-07
申请号：US14579660
申请日：2014-12-22
IPC分类号： G06F1/3296 , G06F1/3287 , H04W52/02 , G06F1/20 , G06F1/3206 , G06F1/3234
摘要： A method of thermal mitigation in a device having a plurality of non-real-time processing units (PUs) and a plurality of real-time PUs, including connecting each of the plurality of real-time PUs and the plurality of non-real-time PUs to a first power supply, and performing thermal mitigation. Performing thermal mitigation includes disconnecting each of the plurality of non-real-time PUs except one of the plurality of non-real-time PUs from the first power supply resulting in an active non-real-time PU, and connecting a second power supply that derives power from the first power supply to the active non-real-time PU, wherein a voltage supplied by the second power supply is less than a voltage supplied by the first power supply.
-
公开(公告)号：US20180267598A1
公开(公告)日：2018-09-20
申请号：US15458843
申请日：2017-03-14
IPC分类号： G06F1/32 , G06F9/44 , G06F21/44 , G06F21/57 , G11C11/406 , G11C11/4074
摘要： A method for reducing power in a system is provided according to aspects of the present disclosure. The system includes a chip, and a volatile memory. The method includes entering a sleep state, and exiting the sleep state. Entering the sleep state includes placing the volatile memory in a self-refresh mode, wherein the volatile memory stores one or more binary images and the volatile memory is powered in the sleep state, and collapsing multiple power supply rails on the chip. Exiting the sleep state includes restoring power to the multiple power supply rails on the chip, taking the volatile memory out of the self-refresh mode, and running the one or more binary images on one or more sub-systems on the chip.
-
公开(公告)号：US10474224B2
公开(公告)日：2019-11-12
申请号：US15458843
申请日：2017-03-14
IPC分类号： G06F1/32 , G06F1/3296 , G06F9/4401 , G06F21/44 , G06F21/57 , G11C11/406 , G11C11/4074
摘要： A method for reducing power in a system is provided according to aspects of the present disclosure. The system includes a chip, and a volatile memory. The method includes entering a sleep state, and exiting the sleep state. Entering the sleep state includes placing the volatile memory in a self-refresh mode, wherein the volatile memory stores one or more binary images and the volatile memory is powered in the sleep state, and collapsing multiple power supply rails on the chip. Exiting the sleep state includes restoring power to the multiple power supply rails on the chip, taking the volatile memory out of the self-refresh mode, and running the one or more binary images on one or more sub-systems on the chip.
-
5.发明授权Circuits and methods providing state information preservation during power saving operations 有权在省电操作期间提供状态信息保存的电路和方法公开(公告)号：US09582068B2
公开(公告)日：2017-02-28
申请号：US14630392
申请日：2015-02-24
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3243 , G06F1/3265 , G06F1/3293 , G06F1/3296 , Y02D10/152 , Y02D10/171
摘要： Methods, systems, and circuits for preserving state information during power saving operations are disclosed. One example embodiment includes a circuit having a processing core, where the processing core includes logic processing circuits as well as circuits (e.g., flip-flops registers) that are used to store state information in the processing core. The logic processing circuits have power connections to a power rail that are subject to a switch, which can disconnect the power connections from the power rail. The circuits that are used to store state information have different power connections that are subject to a different switch. Therefore, the logic processing circuits and the state information circuits can be separately power-collapsed.
摘要翻译： 公开了用于在省电操作期间保持状态信息的方法，系统和电路。 一个示例实施例包括具有处理核心的电路，其中处理核心包括逻辑处理电路以及用于在处理核心中存储状态信息的电路（例如，触发器寄存器）。 逻辑处理电路具有经受切换的电力轨的电力连接，这可以将电力连接从电力轨道断开。 用于存储状态信息的电路具有不同的电源连接，这些电源连接受不同的开关的影响。 因此，逻辑处理电路和状态信息电路可以单独断电。
-
公开(公告)号：US11340689B2
公开(公告)日：2022-05-24
申请号：US16674494
申请日：2019-11-05
IPC分类号： G06F1/3287 , G06F1/3296 , H04W52/02 , G06F1/3234 , G06F1/20 , G06F1/3206
摘要： A method of thermal mitigation in a device having a plurality of non-real-time processing units (PUs) and a plurality of real-time PUs, including connecting each of the plurality of real-time PUs and the plurality of non-real-time PUs to a first power supply, and performing thermal mitigation. Performing thermal mitigation includes disconnecting each of the plurality of non-real-time PUs except one of the plurality of non-real-time PUs from the first power supply resulting in an active non-real-time PU, and connecting a second power supply that derives power from the first power supply to the active non-real-time PU, wherein a voltage supplied by the second power supply is less than a voltage supplied by the first power supply.
-
公开(公告)号：US20200073468A1
公开(公告)日：2020-03-05
申请号：US16674494
申请日：2019-11-05
IPC分类号： G06F1/3287 , G06F1/3296 , H04W52/02 , G06F1/3234 , G06F1/20 , G06F1/3206
摘要： A method of thermal mitigation in a device having a plurality of non-real-time processing units (PUs) and a plurality of real-time PUs, including connecting each of the plurality of real-time PUs and the plurality of non-real-time PUs to a first power supply, and performing thermal mitigation. Performing thermal mitigation includes disconnecting each of the plurality of non-real-time PUs except one of the plurality of non-real-time PUs from the first power supply resulting in an active non-real-time PU, and connecting a second power supply that derives power from the first power supply to the active non-real-time PU, wherein a voltage supplied by the second power supply is less than a voltage supplied by the first power supply.
-
公开(公告)号：US20160179180A1
公开(公告)日：2016-06-23
申请号：US14579660
申请日：2014-12-22
IPC分类号： G06F1/32
摘要： A method of thermal mitigation in a device having a plurality of non-real-time processing units (PUs) and a plurality of real-time PUs, including connecting each of the plurality of real-time PUs and the plurality of non-real-time PUs to a first power supply, and performing thermal mitigation. Performing thermal mitigation includes disconnecting each of the plurality of non-real-time PUs except one of the plurality of non-real-time PUs from the first power supply resulting in an active non-real-time PU, and connecting a second power supply that derives power from the first power supply to the active non-real-time PU, wherein a voltage supplied by the second power supply is less than a voltage supplied by the first power supply.
摘要翻译： 一种具有多个非实时处理单元（PU）和多个实时PU的设备中的热缓解方法，包括连接多个实时PU和多个非实时处理单元 时间PU到第一电源，并执行热减轻。 执行热减轻包括从第一电源断开除了多个非实时PU中的一个以外的多个非实时PU中的每一个，导致活动的非实时PU，并且连接第二电源 其将来自所述第一电源的功率从所述有源非实时PU导出，其中由所述第二电源提供的电压小于由所述第一电源提供的电压。
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.014 秒)
