公开(公告)号：US20180173631A1

公开(公告)日：2018-06-21

申请号：US15594631

申请日：2017-05-14

Applicant: QUALCOMM Incorporated

Inventor： Thomas Andrew SARTORIUS ,  James Norris DIEFFENDERFER ,  Thomas Philip SPEIER ,  Michael Scott MCILVAINE ,  Michael William MORROW

IPC: G06F12/0862 ,  G06F17/30

CPC classification number: G06F12/0862 ,  G06F16/24558 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: Systems and methods are directed to prefetch mechanisms involving non-equal magnitude stride values. A non-equal magnitude functional relationship between successive stride values, may be detected, wherein the stride values are based on distances between target addresses of successive load instructions. At least a next stride value for prefetching data, may be determined, wherein the next stride value is based on the non-equal magnitude functional relationship and a previous stride value. Data prefetch may be from at least one prefetch address calculated based on the next stride value and a previous target address. The non-equal magnitude functional relationship may include a logarithmic relationship corresponding to a binary search algorithm.

公开(公告)号：US20150019843A1

公开(公告)日：2015-01-15

申请号：US14091340

申请日：2013-11-27

Applicant: QUALCOMM Incorporated

Inventor： Anil KRISHNA ,  Sandeep S. NAVADA ,  Niket K. CHOUDHARY ,  Michael Scott MCILVAINE ,  Thomas Andrew SARTORIUS ,  Rodney Wayne SMITH ,  Kenneth Alan DOCKSER

IPC: G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3861

Abstract: A method and apparatus for allowing an out-of-order processor to reuse an in-use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and/or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed or disallowed to be written into a physical register.

Abstract translation: 本文公开了一种允许无序处理器重用使用中物理寄存器的方法和装置。 该方法和装置使用诸如重命名映射表（RMT）和物理寄存器文件（PRF）中的令牌和/或其他标识符的标识符来指示是否允许或不允许将指令结果写入物理寄存器。

公开(公告)号：US20170255569A1

公开(公告)日：2017-09-07

申请号：US15057121

申请日：2016-03-01

Applicant: QUALCOMM Incorporated

Inventor： Thomas Andrew SARTORIUS ,  James Norris DIEFFENDERFER ,  Michael William MORROW ,  Jeffrey Todd BRIDGES ,  Michael Scott MCILVAINE ,  Rodney Wayne SMITH ,  Kenneth Alan DOCKSER ,  Thomas Philip SPEIER

IPC: G06F12/12 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/123 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/604 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/684

Abstract: Systems and methods for managing access to a cache relate to determining one or more execute permissions associated with a write-address of a write-request to the cache. The cache may be a unified cache for storing data as well as instructions. If there is a write-miss in the cache for the write-request, a cache controller may determine whether to implement a write-allocate policy or a write-no-allocate policy for servicing the write-miss, based on the one or more execute permissions. The one or more execute permissions can relate to a privilege level associated with the write-address. Execute permissions of a producing agent which generated the write-request and an execute permission of a consuming agent which can execute from the write-address may be based on the privilege levels of the producing agent and the consuming agent, respectively.

公开(公告)号：US20170091117A1

公开(公告)日：2017-03-30

申请号：US14865049

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Harold Wade CAIN, III ,  Derek Robert HOWER ,  Raguram DAMODARAN ,  Thomas Andrew SARTORIUS

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/121 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0888 ,  G06F12/0895 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/621 ,  Y02D10/13

Abstract: A cache fill line is received, including an index, a thread identifier, and cache fill line data. The cache is probed, using the index and a different thread identifier, for a potential duplicate cache line. The potential duplicate cache line includes cache line data and the different thread identifier. Upon the cache fill line data matching the cache line data, duplication is identified. The potential duplicate cache line is set as a shared resident cache line, and the thread share permission tag is set to a permission state.

公开(公告)号：US20170083333A1

公开(公告)日：2017-03-23

申请号：US14859356

申请日：2015-09-21

Applicant: QUALCOMM Incorporated

Inventor： Niket Kumar CHOUDHARY ,  Michael Scott MCILVAINE ,  Daren Eugene STREETT ,  Vimal Kodandarama REDDY ,  Shekhar Shashi SRIKANTAIAH ,  Sandeep Suresh NAVADA ,  Robert Douglas CLANCY ,  James Norris DIEFFENDERFER ,  Thomas Andrew SARTORIUS

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30058 ,  G06F9/3808 ,  G06F12/0875 ,  G06F2212/452

Abstract: Systems and methods pertain to a branch target instruction cache (BTIC) of a processor. The BTIC is configured to store one or more branch target instructions at branch target addresses of branch instructions executable by the processor. At least one of the branch target instructions stored in the BTIC is a conditional branch instruction. Branch prediction techniques for predicting the direction of the conditional branch instruction allow one or more instructions following the conditional branch instruction, as well as a branch target address of the conditional branch instruction to also be stored in the BTIC.

公开(公告)号：US20160342530A1

公开(公告)日：2016-11-24

申请号：US14716947

申请日：2015-05-20

Applicant: QUALCOMM Incorporated

Inventor： Henry Arthur PELLERIN, III ,  Thomas Philip SPEIER ,  Thomas Andrew SARTORIUS ,  Michael William MORROW ,  James Norris DIEFFENDERFER ,  Kenneth Alan DOCKSER ,  Michael Scott MCILVAINE

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/401 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract translation: 存储器结构使用索引标签压缩结构压缩存储器标签的一部分。 存储器标签的一组较高位可以存储在索引标签压缩结构中，其中较高位的集合由索引值标识。 标签阵列存储存储器标签的一组较低位，以及标识在存储标签的较高位的集合的标签压缩结构中的条目的索引值。 存储器标签可以包括存储在数据阵列中的数据元素的存储器地址的至少一部分。