公开(公告)号：US20190259780A1

公开(公告)日：2019-08-22

申请号：US16402713

申请日：2019-05-03

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Daniel Daeik KIM ,  Matthew Michael NOWAK ,  Jonghae KIM ,  Changhan Hobie YUN ,  Je-Hsiung Jeffrey LAN ,  David Francis BERDY

IPC: H01L27/12 ,  H01L23/498 ,  H01L21/306 ,  H01L23/66 ,  H01L27/088 ,  H01L21/304 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US20160013133A1

公开(公告)日：2016-01-14

申请号：US14330950

申请日：2014-07-14

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Matthew Michael NOWAK ,  Jeffrey Junhao XU

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/7682 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.

Abstract translation: 系统和方法涉及包括集成电路的半导体器件，其中集成电路至少包括包含两条或更多条钨线的至少一条第一层和至少两条钨线之间的至少一个气隙，所述气隙减少 电容。 插入器耦合到集成电路，以减少两个或多个钨线和至少一个气隙的应力。 层叠封装基板可以附接到插入件，使得插入件被构造成吸收由层压封装基板和插入件之间的热膨胀系数（CTE）失配引起的机械应力，并保护气隙免受机械应力。

公开(公告)号：US20170373175A1

公开(公告)日：2017-12-28

申请号：US15192773

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Gengming TAI ,  Je-Hsiung LAN ,  Matthew Michael NOWAK ,  Miguel MIRANDA CORBALAN ,  Steve FANELLI

IPC: H01L29/737 ,  H01L23/31 ,  H01L29/08 ,  H01L29/66

Abstract: Disclosed is a heterojunction bipolar transistor, and method of manufacturing the same, including an emitter having a conductive emitter contact coupled to a first side of the emitter, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter, a collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter, a first conductive base contact coupled to the base, and a conductive collector contact coupled to the collector on the side of the collector opposite the emitter and substantially parallel to the first conductive base contact.

公开(公告)号：US20170360316A1

公开(公告)日：2017-12-21

申请号：US15186347

申请日：2016-06-17

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Matthew Michael NOWAK ,  Kenneth KASKOUN ,  Eugene DANTSKER ,  Russel Allyn MARTIN

IPC: A61B5/024 ,  A61B5/1455 ,  A61B5/145 ,  A61B5/00

CPC classification number: A61B5/02433 ,  A61B5/14532 ,  A61B5/14551 ,  A61B5/14552 ,  A61B5/681 ,  A61B5/6823 ,  A61B5/6824 ,  A61B5/6828 ,  A61B5/7278 ,  A61B5/742 ,  A61B5/7475 ,  A61B2560/0214 ,  A61B2560/0475 ,  A61B2562/04 ,  A61B2562/046 ,  A61B2562/164

Abstract: Examples of monolithic integrated emitter-detector array in a flexible substrate for biometric sensing and associated devices and methods are disclosed. One disclosed example device includes a flexible substrate; a first array of emitters embedded in the flexible substrate, the first array of emitters configured to emit first electromagnetic (EM) signals; a first array of detectors embedded in the flexible substrate, the first array of detectors configured to detect reflections of the first EM signals; a first scanning circuit coupled to the first array of emitters, the first scanning circuit configured to selectively activate individual emitters of the first array of emitters; and a first sensing circuit coupled to individual detectors of the first array of detectors, the first sensing circuit configured to receive a detection signal from at least one of the detectors of the first array of detectors.

公开(公告)号：US20160254236A1

公开(公告)日：2016-09-01

申请号：US14633934

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  David Francis BERDY ,  Chengjie ZUO ,  Jonghae KIM ,  Matthew Michael NOWAK

IPC: H01L23/60 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/60 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/00 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.

Abstract translation: 接地屏蔽通过具有导电表面的导体屏蔽来实现，导电表面立即围绕多芯片模块或器件（例如具有倒装芯片（FC）凸块的多芯片模块或器件）中的单个芯片。 多芯片模块或设备内的单个芯片之间的模块间屏蔽通过由紧邻每个芯片的导体屏蔽表面提供的电磁或射频信号（RF）隔离来实现。 导体屏蔽件直接连接到基板或插入件的一个或多个接地导体部分，以确保可靠的接地。

公开(公告)号：US20160071847A1

公开(公告)日：2016-03-10

申请号：US14480156

申请日：2014-09-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  Matthew Michael NOWAK ,  Choh Fei YEAP ,  Roawen CHEN

IPC: H01L27/088 ,  G06F17/50

CPC classification number: H01L27/0886 ,  G03F7/00 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0207

Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.

Abstract translation: 根据本公开的一个方面的用于半节点缩放电路布局的方法包括裸片上的垂直设备。 该方法包括降低管芯上的垂直装置的翅片间距和栅极间距。 该方法还包括缩放波长以限定电路布局的至少一个缩小区域几何图案。

公开(公告)号：US20190341381A1

公开(公告)日：2019-11-07

申请号：US15970618

申请日：2018-05-03

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Matthew Michael NOWAK

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/737 ,  H01L29/93 ,  H01L29/205 ,  H01L21/8249

Abstract: A semiconductor device comprises a complementary metal oxide semiconductor (CMOS) device and a heterojunction bipolar transistor (HBT) integrated on a single die. The CMOS device may comprise silicon. The HBT may comprise III-V materials. The semiconductor device may be employed in a radio frequency front end (RFFE) module to reduce size and parasitics of the RFFE module and to provide cost and cycle time savings.

公开(公告)号：US20160254237A1

公开(公告)日：2016-09-01

申请号：US14634148

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  David Francis BERDY ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  Chengjie ZUO ,  Jonghae KIM ,  Matthew Michael NOWAK

IPC: H01L23/60 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/60 ,  H01L21/568 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/00 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/04105

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package (FOWLP) module or device. Intra-module shielding between individual chips within the FOWLP module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a FOWLP to ensure reliable grounding.

Abstract translation: 接地屏蔽通过具有导电表面的导体屏蔽来实现，该导电屏蔽立即围绕扇出晶片级封装（FOWLP）模块或器件中的各个芯片。 FOWLP模块或设备内各个芯片之间的模块内屏蔽是通过电磁或无线电信号（RF）隔离来实现的，该隔离由导体屏蔽的表面立即围绕每个芯片。 导体屏蔽层直接连接到FOWLP的一个或多个接地导体部分，以确保可靠的接地。

公开(公告)号：US20150201495A1

公开(公告)日：2015-07-16

申请号：US14155187

申请日：2014-01-14

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  Changhan Hobie YUN ,  Jonghae KIM ,  Matthew Michael NOWAK

IPC: H05K1/14 ,  H05K3/06 ,  H05K1/18

CPC classification number: H05K1/141 ,  H01F17/0006 ,  H01F2017/0086 ,  H01L23/49833 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/042 ,  H05K2201/1003 ,  Y10T29/4902 ,  H01L2924/00

Abstract: An integrated circuit device includes a first substrate supporting a pair of conductive interconnects, for example pillars. The device also includes a second substrate on the pair of conductive interconnects. The pair of conductive interconnects is arranged to operate as a first 3D solenoid inductor. The device further includes a conductive trace coupling the pair of conductive interconnects to each other.

Abstract translation: 集成电路装置包括支撑一对导电互连（例如柱）的第一基板。 该装置还包括一对导电互连上的第二基板。 一对导电互连件布置成作为第一3D螺线管电感器工作。 该装置还包括将一对导电互连件彼此耦合的导电迹线。

公开(公告)号：US20190132942A1

公开(公告)日：2019-05-02

申请号：US15798071

申请日：2017-10-30

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Jonghae KIM ,  Xiaoju YU ,  Mario Francisco VELEZ ,  Wei-Chuan CHEN ,  Niranjan Sunil MUDAKATTE ,  Matthew Michael NOWAK ,  Christian HOFFMANN ,  Rodrigo PACHER FERNANDES ,  Manuel HOFER ,  Peter BAINSCHAB ,  Edgar SCHMIDHAMMER ,  Stefan Leopold HATZL

IPC: H05K1/02 ,  H03H9/02 ,  H05K3/32

CPC classification number: H05K1/0233 ,  H03H3/02 ,  H03H3/08 ,  H03H9/02086 ,  H03H9/0547 ,  H03H9/1014 ,  H03H9/1071 ,  H05K3/32

Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.