公开(公告)号：US10304957B2

公开(公告)日：2019-05-28

申请号：US15264519

申请日：2016-09-13

Applicant: QUALCOMM Incorporated

Inventor： Ukjin Roh ,  Shashank Ekbote

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/165 ,  H01L29/167 ,  H01L21/265 ,  H01L29/08 ,  H01L29/66

Abstract: Selective epitaxial growth is used to form a hetero-structured source/drain region to fill an etched recess in a silicon fin for an n-type FinFET device.

公开(公告)号：US20180076326A1

公开(公告)日：2018-03-15

申请号：US15264519

申请日：2016-09-13

Applicant: QUALCOMM Incorporated

Inventor： Ukjin Roh ,  Shashank Ekbote

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/167 ,  H01L21/265 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02636 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Selective epitaxial growth is used to form a hetero-structured source/drain region to fill an etched recess in a silicon fin for an n-type FinFET device.

公开(公告)号：US20180061943A1

公开(公告)日：2018-03-01

申请号：US15454099

申请日：2017-03-09

Applicant: QUALCOMM Incorporated

Inventor： Youn Sung Choi ,  Ukjin Roh ,  Shashank Ekbote

IPC: H01L29/06 ,  H01L23/535 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/413 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/66606 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/7851

Abstract: Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate.

公开(公告)号：US09882051B1

公开(公告)日：2018-01-30

申请号：US15266840

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Ukjin Roh ,  Youn Sung Choi ,  Shashank Ekbote

IPC: H01L29/78 ,  H01L27/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/08 ,  H01L21/02 ,  H01L29/417 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L21/02271 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: Fin Field Effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions are disclosed. In one aspect, a FinFET is provided that includes a substrate and a Fin disposed over the substrate. The Fin includes a source, a drain, and a channel region between the source and drain. A gate is disposed around the channel region. To apply stress to the channel region, a first dielectric material layer is disposed over the substrate and adjacent to one side of the Fin. A second dielectric material layer is disposed over the substrate and adjacent to another side of the Fin. The dielectric material layers apply stress along the Fin, including the channel region. The level of stress applied by the dielectric material layers is not dependent on the volume of each layer.

公开(公告)号：US09634138B1

公开(公告)日：2017-04-25

申请号：US15245777

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Youn Sung Choi ,  Ukjin Roh ,  Shashank Ekbote

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/41

CPC classification number: H01L29/66545 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/413 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/66606 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/7851

Abstract: Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate.

公开(公告)号：US10861852B2

公开(公告)日：2020-12-08

申请号：US16180349

申请日：2018-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Shashank Ekbote ,  Periannan Chidambaram

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/08 ,  H01L29/06 ,  H01L23/522 ,  H01L25/07 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/822 ,  H01L23/528

Abstract: A 3D vertically integrated FET for CMOS cell circuits is disclosed. Vertically integrating FETs for a 3D cell circuit reduces the footprint size of an IC chip. To reduce a CMOS cell circuit footprint, a PFET and an NFET are vertically integrated by stacking a second semiconductor layer including a second FET above a first semiconductor layer including a first FET, such that the channel structure of the second FET overlaps the channel structure of the first FET. The first FET may be an NFET, and the second FET may be a PFET, or vice versa. The longitudinal axis of the first FET channel structure may extend in a first plane parallel to a second plane including the longitudinal axis of the second FET channel structure. The longitudinal axes may be parallel or at an angle to each other, such that the second channel structure overlaps the first channel structure.

公开(公告)号：US20200144264A1

公开(公告)日：2020-05-07

申请号：US16180349

申请日：2018-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Shashank Ekbote ,  Periannan Chidambaram

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/08 ,  H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/822 ,  H01L25/07

Abstract: A 3D vertically integrated FET for CMOS cell circuits is disclosed. Vertically integrating FETs for a 3D cell circuit reduces the footprint size of an IC chip. To reduce a CMOS cell circuit footprint, a PFET and an NFET are vertically integrated by stacking a second semiconductor layer including a second FET above a first semiconductor layer including a first FET, such that the channel structure of the second FET overlaps the channel structure of the first FET. The first FET may be an NFET, and the second FET may be a PFET, or vice versa. The longitudinal axis of the first FET channel structure may extend in a first plane parallel to a second plane including the longitudinal axis of the second FET channel structure. The longitudinal axes may be parallel or at an angle to each other, such that the second channel structure overlaps the first channel structure.

公开(公告)号：US20180350819A1

公开(公告)日：2018-12-06

申请号：US15609505

申请日：2017-05-31

Applicant: QUALCOMM Incorporated

Inventor： Youn Sung Choi ,  Samit Sengupta ,  Shashank Ekbote

IPC: H01L27/11 ,  H01L29/10 ,  H01L23/528 ,  H01L27/092 ,  H01L23/532 ,  H01L29/49 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/0207

Abstract: Aspects for reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells are disclosed herein. An exemplary SRAM strap cell includes a P-type doped well (Pwell) tap electrically coupled to a first supply rail to distribute a first supply voltage to a Pwell region of corresponding SRAM bit cell rows. The SRAM strap cell also includes an N-type doped well (Nwell) tap electrically coupled to a second supply rail to distribute a second supply voltage to an Nwell region of corresponding SRAM bit cell rows. In one exemplary aspect, the Nwell tap can include multiple supply contacts used to couple the second supply rail to the SRAM strap cell to reduce mechanical stress in the Nwell tap. In another exemplary aspect, the Pwell tap can include non-active gates disposed across multiple Fins to stabilize the Fins and reduce or avoid mechanical stress in the Pwell tap.

公开(公告)号：US10062768B2

公开(公告)日：2018-08-28

申请号：US15454099

申请日：2017-03-09

Applicant: QUALCOMM Incorporated

Inventor： Youn Sung Choi ,  Ukjin Roh ,  Shashank Ekbote

IPC: H01L29/66 ,  H01L29/06 ,  H01L23/535 ,  H01L29/78 ,  H01L29/423 ,  H01L29/772

Abstract: Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate.

公开(公告)号：US09853152B1

公开(公告)日：2017-12-26

申请号：US15266840

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Ukjin Roh ,  Youn Sung Choi ,  Shashank Ekbote

IPC: H01L29/78 ,  H01L27/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/08 ,  H01L21/02 ,  H01L29/417 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L21/02271 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: Fin Field Effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions are disclosed. In one aspect, a FinFET is provided that includes a substrate and a Fin disposed over the substrate. The Fin includes a source, a drain, and a channel region between the source and drain. A gate is disposed around the channel region. To apply stress to the channel region, a first dielectric material layer is disposed over the substrate and adjacent to one side of the Fin. A second dielectric material layer is disposed over the substrate and adjacent to another side of the Fin. The dielectric material layers apply stress along the Fin, including the channel region. The level of stress applied by the dielectric material layers is not dependent on the volume of each layer.