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公开(公告)号：US20220100421A1
公开(公告)日：2022-03-31
申请号：US17034880
申请日：2020-09-28
Applicant: Quanta Computer Inc.
Inventor： Chih-Chia HUANG , Po-Wei HUANG , Te-Hsien LAI , Yi-Hung SHEN
IPC: G06F3/06
Abstract: A system and method for simultaneously programming flash memory devices in a computing device is disclosed. The computing system includes a switching unit that includes an input and multiple outputs. The switching unit connects the input to one or more of the outputs. Each of the flash memory devices is coupled to one of the outputs of the switching unit. A control bus is coupled to the switching unit. The control bus carries a control signal to select one or more of the outputs for connection to the input. A programming interface bus is coupled to the input of the switching unit. A controller is coupled to the control bus and the programming interface bus. The controller selects the memory devices for providing programming over the programming interface bus.
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公开(公告)号：US20190242688A1
公开(公告)日：2019-08-08
申请号：US15887337
申请日：2018-02-02
Applicant: QUANTA COMPUTER INC.
Inventor： Chih-Chia HUANG , Cheng-Shian YAN
CPC classification number: G01B7/003 , G01R33/02 , H05K7/20172
Abstract: A computing device includes a first component comprising a magnetic field sensor with a sensing region and a second component comprising a magnetic portion. The computing device also includes a controller communicatively coupled to the magnetic field sensor. In the computing device, the second component is movable between a first position relative to the first component, and one or more second positions relative to the first component, whereby the magnetic portion is positioned in the sensing region when the sensing portion is in the first position. The magnetic field sensor is configured for generating one or more first signals in response to detecting the magnetic portion within the sensing region. The controller is configured for generating a second signal in response to the first signals indicating the second component is in the first position.
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公开(公告)号：US20190122015A1
公开(公告)日：2019-04-25
申请号：US15788544
申请日：2017-10-19
Applicant: QUANTA COMPUTER INC.
Inventor： Chih-Chia HUANG , Chin-Lung SU , Hao-Yu CHAN , Ming-Chih HSIAO
IPC: G06K7/10
CPC classification number: G06K7/10356 , G06F1/183 , G06K7/10475 , H05K7/1498
Abstract: Methods and apparatuses are disclosed for managing components within a server using radiofrequency communications. The methods and apparatuses disclosed employ a server having a chassis with a plurality of slots. Each slot of the plurality of slots is configured to connect a removable electronic component to the chassis. The server also includes a controller configured to manage the removable electronic components connected to the chassis. The server also includes at least one RFID reader communicatively connected to the controller. The at least one RFID reader is configured to interrogate one or more RFID tags of the removable electronic components connected to the chassis and provide information from the one or more RFID tags to the controller.
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公开(公告)号：US20170244640A1
公开(公告)日：2017-08-24
申请号：US15049941
申请日：2016-02-22
Applicant: Quanta Computer Inc.
Inventor： Li-Min LIN , Chih-Chia HUANG , Ying-Chin HUANG
IPC: H04L12/803 , H04L12/947 , H04L12/931
CPC classification number: H04L47/125 , H04L43/08 , H04L49/25 , H04L49/70 , H04L67/1004
Abstract: A system for offloading management controller traffic includes a data port, an out-of-band port, and a leaf switch. The leaf switch includes a switch application-specific integrated circuit (ASIC) and an unmanaged chip directly connected to the switch ASIC. The switch ASIC is configured to direct data traffic to the data port and offload baseboard management controller (BMC) traffic to the unmanaged chip. The unmanaged chip is configured to direct the BMC traffic to the out-of-band port.
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Patent Agency Ranking
公开(公告)号：US20180203768A1
公开(公告)日：2018-07-19
申请号：US15410177
申请日：2017-01-19
Applicant: QUANTA COMPUTER INC.
Inventor： Chih-Chia HUANG , Chin-Lung SU , Tsai-I YEN
CPC classification number: G06F11/1441 , G06F11/0721 , G06F11/0757 , G06F11/079 , G06F11/3024 , G06F11/3055 , G06F11/3495 , G06F2201/805 , G06F2201/81 , G06F2201/86 , H04L41/0672 , H04L41/24 , H04L41/26
Abstract: The present technology provides a system and method for smartly resetting a hang device of a server system based upon a Wake-on-Lan (WoL) message and status of the hang device. The system comprises a management device, a switch, a physical layer (PHY) coupled to a network, a network interface (NIC), a monitoring device and a delay circuit. The PHY is coupled to the network to receive network packets that includes a WoL message. The monitoring device is configured to receive status information from the management device and the WoL message, and reset the management device based upon received information.
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公开(公告)号：US20180203499A1
公开(公告)日：2018-07-19
申请号：US15409307
申请日：2017-01-18
Applicant: QUANTA COMPUTER INC.
Inventor： Chih-Chia HUANG , Li-Min LIN , Ching-Jen FANG , Tsai-I YEN
CPC classification number: G06F11/3055 , G06F1/30 , G06F11/30 , G06F11/3051
Abstract: The present technology provides a system and method for selectively powering down active component(s) of a system based upon PSU status and power demand of the system. The present technology enables the system in operation as long as the system has at least one operative PSU. The system comprises a plurality of active components, two or more PSUs, a management device and a hardware device. The hardware device can receive status information of the two or more PSUs and system power demand information. In response to determining that the power capacity of the two or more PSUs is less than the power demand of the system, the hardware device can determine status of the PSUs. In response to determining that the status of at least one PSU is not ok, the hardware device can turn off at least one of the plurality of active components based upon a power-down sequence.
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公开(公告)号：US20170147453A1
公开(公告)日：2017-05-25
申请号：US14950519
申请日：2015-11-24
Applicant: Quanta Computer Inc.
Inventor： Chih-Chia HUANG , Hao-Yu CHAN , Te-Hsien LAI , Tsai-I YEN
IPC: G06F11/20
CPC classification number: G06F11/2007 , G06F11/0706 , G06F11/0793 , G06F2201/805 , G06F2201/85
Abstract: A system and method of using a baseboard management controller (BMC) to detect a fault on a communication bus. The BMC is connected to and monitors the operation of the communication bus. The BMC automatically detects a communication bus hang and reports bus hang to the host. The BMC attempts to access the communication bus. If the BMC can access the communication bus, the BMC then resets all of the devices connected to the communication bus. The BMC then attempts to contact components connected to the devices. If a component is not accessible via its communication device, the BMC blocks the channel used by the component and reports that information. Once the BMC detects that the component has been removed, the BMC attempts to recover the channel via the I2C/SM bus for use by the computer network.
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公开(公告)号：US20190235592A1
公开(公告)日：2019-08-01
申请号：US15886418
申请日：2018-02-01
Applicant: QUANTA COMPUTER INC.
Inventor： Chih-Chia HUANG , Hao-Yu CHAN , Tsai-I YEN
Abstract: Systems and methods are described for improved cooling behavior in computer systems using fan-based cooling systems. In particular, the systems and methods utilize two types of techniques can be used for providing improved cooling behavior: hardware-based techniques and software-based techniques. These techniques can be used separately or in combination.
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公开(公告)号：US20180203779A1
公开(公告)日：2018-07-19
申请号：US15408196
申请日：2017-01-17
Applicant: QUANTA COMPUTER INC.
Inventor： Chih-Chia HUANG , Ming-Chih HSIAO
CPC classification number: G06F11/3027 , G06F11/0703 , G06F11/0715 , G06F11/0751 , G06F11/3048 , G06F11/3051 , G06F13/4282
Abstract: A method of monitoring I2C bus status using a Baseboard Management Controller (BMC) and a hardware watchdog (HW) circuit is provided. The method includes detecting, using the HW circuit, a failure of an I2C bus and determining if the HW circuit can auto reset I2C devices on the I2C bus. The method also includes, if it is determined that the HW circuit can auto reset the I2C devices on the I2C bus, resetting, using the HW circuit, the I2C devices, and if it is determined that the HW circuit cannot auto reset the I2C devices on the I2C bus, reporting, using the HW circuit, detected failure to the BMC. The method further includes processing, using the BMC, the detected failure.
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