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    Hardware acceleration for a software transactional memory system
    4.
    发明授权
    Hardware acceleration for a software transactional memory system 有权
    软件交易内存系统的硬件加速

    公开(公告)号：US07958319B2

    公开(公告)日：2011-06-07

    申请号：US11926423

    申请日：2007-10-29

    申请人： Bratin Saha ,  Ali-Reza Adl-Tabatabai ,  Quinn A. Jacobson

    发明人： Bratin Saha ,  Ali-Reza Adl-Tabatabai ,  Quinn A. Jacobson

    IPC分类号： G06F13/376

    CPC分类号： G06F13/4243 ,  G06F9/3834 ,  G06F9/466 ,  G06F9/526

    摘要： A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.

    摘要翻译： 一种用于加速事务执行的方法和装置。 只有在事务中第一次访问共享内存条时，才会调用/执行与事务中的内存访问引用的共享内存条相关联的障碍。 提供诸如事务字段/事务位之类的硬件支持来确定访问是否是在事务挂起期间对共享存储器行的第一次访问。 另外，在积极的操作模式中，代表存储在共享存储器行中的元素的版本号的版本号在保存验证成本的承诺时不被存储和验证。 而且，即使在谨慎的模式下，存储版本号以启用验证，如果在执行交易期间没有发生访问的共享内存条的驱逐，则可能不会产生验证成本。

    HANDLING PRECOMPILED BINARIES IN A HARDWARE ACCELERATED SOFTWARE TRANSACTIONAL MEMORY SYSTEM
    5.
    发明申请
    HANDLING PRECOMPILED BINARIES IN A HARDWARE ACCELERATED SOFTWARE TRANSACTIONAL MEMORY SYSTEM 有权
    在硬件加速软件交易存储系统中处理预先确定的二进制

    公开(公告)号：US20150040111A1

    公开(公告)日：2015-02-05

    申请号：US14271024

    申请日：2014-05-06

    申请人： Bratin Saha ,  Ali-Reza Adl-Tabatabai ,  Quinn A. Jacobson

    发明人： Bratin Saha ,  Ali-Reza Adl-Tabatabai ,  Quinn A. Jacobson

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F12/08

    CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/467 ,  G06F12/0837 ,  G06F2212/62

    摘要： A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field associated with a memory location referenced by the access is checked. In response to the memory location representing a previous similar access within the transaction, the access is performed without access barriers. However, if the annotation field is in a default state representing no previous access during a pendancy of the transaction, then a mode of the processor is determined. If the processor mode is in implicit mode, an access handler/barrier is asynchronously executed. Conversely, in an explicit mode, a flag is set instead of asynchronously executing the handler. In addition, during compilation convert explicit and convert implicit instructions are inserted to intelligently convert modes for precompiled and newly compiled binaries. Furthermore, new versions of newly compiled functions may be inserted to provide strong atomicity between previously and newly compiled functions.

    摘要翻译： 这里描述了使用预编译二进制文件实现软件事务存储器（STM）的方法和装置。 在事务中遇到访问操作时，检查与由访问引用的存储器位置相关联的注释字段。 响应于表示事务内先前类似访问的存储器位置，访问被执行而没有访问障碍。 然而，如果注释字段处于表示在事务的挂起期间没有先前访问的默认状态，则确定处理器的模式。 如果处理器模式处于隐式模式，则异步执行访问处理程序/障碍。 相反，在显式模式下，设置标志而不是异步执行处理程序。 此外，在编译期间，转换显式和转换隐式指令将被智能地转换为预编译和新编译的二进制文件的模式。 此外，可以插入新版本的新编译的函数，以便在先前和新编译的函数之间提供强大的原子性。

    Hardware acceleration for a software transactional memory system
    8.
    发明授权
    Hardware acceleration for a software transactional memory system 有权
    软件交易内存系统的硬件加速

    公开(公告)号：US07725662B2

    公开(公告)日：2010-05-25

    申请号：US11926440

    申请日：2007-10-29

    申请人： Bratin Saha ,  Ali-Reza Adl-Tabatabai ,  Quinn A. Jacobson

    发明人： Bratin Saha ,  Ali-Reza Adl-Tabatabai ,  Quinn A. Jacobson

    IPC分类号： G06F13/376

    CPC分类号： G06F13/4243 ,  G06F9/3834 ,  G06F9/466 ,  G06F9/526

    摘要： A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.

    摘要翻译： 一种用于加速事务执行的方法和装置。 只有在事务中第一次访问共享内存条时，才会调用/执行与事务中的内存访问引用的共享内存条相关联的障碍。 提供诸如事务字段/事务位之类的硬件支持来确定访问是否是在事务挂起期间对共享存储器行的第一次访问。 另外，在积极的操作模式中，代表存储在共享存储器行中的元素的版本号的版本号在保存验证成本的承诺时不被存储和验证。 而且，即使在谨慎的模式下，存储版本号以启用验证，如果在执行交易期间没有发生访问的共享内存条的驱逐，则可能不会产生验证成本。