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公开(公告)号：US12026104B2
公开(公告)日：2024-07-02
申请号：US17438844
申请日：2020-03-19
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Craig E. Hampel
CPC classification number: G06F13/1605 , G06F7/483
Abstract: Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.
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公开(公告)号：US20230333927A1
公开(公告)日：2023-10-19
申请号：US18095341
申请日：2023-01-10
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Craig E. Hampel
CPC classification number: G06F11/1004 , G06F11/0703 , G06F11/073 , G06F11/1679 , H03M13/09
Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation
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公开(公告)号：US11755508B2
公开(公告)日：2023-09-12
申请号：US17507588
申请日：2021-10-21
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely Tsern , John Eric Linstadt , Thomas J. Giovannini , Craig E. Hampel , Scott C. Best , John Yan
IPC: G06F13/16
CPC classification number: G06F13/1678 , G06F13/1673 , G06F13/1694
Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.
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公开(公告)号：US11579965B2
公开(公告)日：2023-02-14
申请号：US17481246
申请日：2021-09-21
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Craig E. Hampel
Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
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公开(公告)号：US11474959B2
公开(公告)日：2022-10-18
申请号：US17228506
申请日：2021-04-12
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Craig E. Hampel
IPC: G06F13/16 , G11C7/10 , G11C5/04 , G11C11/4096 , G06F13/40 , G11C11/408 , G11C11/4093
Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.
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Patent Agency Ranking
公开(公告)号：US11258522B2
公开(公告)日：2022-02-22
申请号：US17024835
申请日：2020-09-18
Applicant: Rambus Inc.
Inventor： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
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公开(公告)号：US11108510B2
公开(公告)日：2021-08-31
申请号：US16861164
申请日：2020-04-28
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC: H04L7/00 , H04L1/24 , H04L7/10 , H04L25/02 , H04L25/12 , G11C29/02 , G11C7/10 , H04L27/00 , G11C7/04 , H04L7/033
Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
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公开(公告)号：US20210044417A1
公开(公告)日：2021-02-11
申请号：US17000182
申请日：2020-08-21
Applicant: Rambus Inc.
Inventor： Bret G. Stott , Craig E. Hampel , Frederick A. Ware
Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.
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公开(公告)号：US20210027825A1
公开(公告)日：2021-01-28
申请号：US16896056
申请日：2020-06-08
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC: G11C11/4076 , G11C7/10 , G06F13/16 , G06F13/40 , G11C5/06 , G11C29/02 , G11C29/50 , G11C8/18 , G11C7/22 , G06F1/10 , G11C11/409 , G11C11/4096 , G06F1/06 , G06F1/12 , G06F3/06
Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.
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公开(公告)号：US10819447B2
公开(公告)日：2020-10-27
申请号：US16692029
申请日：2019-11-22
Applicant: Rambus Inc.
Inventor： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
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