公开(公告)号：US20150249145A1

公开(公告)日：2015-09-03

申请号：US14634736

申请日：2015-02-28

Applicant: Renesas Electronics Corporation

Inventor： Hiromasa YOSHIMORI ,  Hirofumi TOKITA

IPC: H01L29/66 ,  H01L21/266 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/115 ,  H01L21/3105

CPC classification number: H01L27/1157 ,  H01L21/266 ,  H01L21/28282 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L23/535 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.

Abstract translation: 提供了具有改进的性能的半导体器件。 在半导体衬底上，通过第一绝缘膜形成虚拟控制栅电极。 在半导体衬底上，用于存储单元的存储栅电极经由具有内部电荷存储部分的第二绝缘膜形成，以便与虚拟控制栅电极相邻。 此时，存储栅电极的高度被调节为低于虚拟控制栅电极的高度。 然后，形成第三绝缘膜，以覆盖虚拟控制栅电极和存储栅电极。 然后，对第三绝缘膜进行抛光以露出虚拟控制栅电极。 此时，存储栅电极不露出。 然后，去除虚拟控制栅电极并用金属栅电极代替。

公开(公告)号：US20180061964A1

公开(公告)日：2018-03-01

申请号：US15792423

申请日：2017-10-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi TOKITA ,  Tamotsu OGATA

IPC: H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: The reliability of a semiconductor device having a nonvolatile memory is improved. The memory cell of the nonvolatile memory is of a split gate type, and has first and second n type semiconductor regions in a semiconductor substrate, a control electrode formed over the substrate between the semiconductor regions via a first insulation film, and a memory gate electrode formed over the substrate between the semiconductor regions via a second insulation film having a charge accumulation part. The SSI method is used for write to the memory cell. During the read operation of the memory cell, the first and second semiconductor regions function as source and drain regions, respectively. The first width of the first sidewall spacer formed adjacent to the side surface of the memory gate electrode is larger than the second width of the second sidewall spacer formed adjacent to the side surface of the control gate electrode.

公开(公告)号：US20160218108A1

公开(公告)日：2016-07-28

申请号：US14973471

申请日：2015-12-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi TOKITA ,  Tamotsu OGATA

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: The reliability of a semiconductor device having a nonvolatile memory is improved. The memory cell of the nonvolatile memory is of a split gate type, and has first and second n type semiconductor regions in a semiconductor substrate, a control electrode formed over the substrate between the semiconductor regions via a first insulation film, and a memory gate electrode formed over the substrate between the semiconductor regions via a second insulation film having a charge accumulation part. The SSI method is used for write to the memory cell. During the read operation of the memory cell, the first and second semiconductor regions function as source and drain regions, respectively. The first width of the first sidewall spacer formed adjacent to the side surface of the memory gate electrode is larger than the second width of the second sidewall spacer formed adjacent to the side surface of the control gate electrode.

Abstract translation: 提高了具有非易失性存储器的半导体器件的可靠性。 非易失性存储器的存储单元是分离栅型，并且在半导体衬底中具有第一和第二n型半导体区域，经由第一绝缘膜形成在半导体区域之间的衬底上的控制电极和存储栅电极 通过具有电荷累积部分的第二绝缘膜在半导体区域之间的衬底上形成。 SSI方法用于写入存储单元。 在存储单元的读取操作期间，第一和第二半导体区域分别用作源区和漏区。 与存储栅电极的侧表面相邻形成的第一侧壁间隔物的第一宽度大于与控制栅电极的侧表面相邻形成的第二侧壁间隔件的第二宽度。

公开(公告)号：US20160079379A1

公开(公告)日：2016-03-17

申请号：US14950850

申请日：2015-11-24

Applicant: Renesas Electronics Corporation

Inventor： Hirofumi TOKITA

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/42364 ,  G11C11/412 ,  G11C11/4125 ,  G11C11/419 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

Abstract: In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.

Abstract translation: 一种n沟道HK / MG晶体管，包括：由包含La和Hf的第一高电介质膜制成的栅极绝缘膜; 以及栅极，其由金属膜和多晶Si膜的叠层膜形成，并且形成在半导体衬底的主表面的有源区中并被由含氧的绝缘膜形成的元件分离部分包围 原子，第二高电介质膜，其含有Hf但其La含量小于第一高介电膜的La含量，形成在乘以元件分离部分的栅电极下面，而不是第一高介电膜。

公开(公告)号：US20150187657A1

公开(公告)日：2015-07-02

申请号：US14657220

申请日：2015-03-13

Applicant: Renesas Electronics Corporation

Inventor： Hirofumi TOKITA

IPC: H01L21/8234

CPC classification number: H01L29/42364 ,  G11C11/412 ,  G11C11/4125 ,  G11C11/419 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

Abstract: In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.

Abstract translation: 一种n沟道HK / MG晶体管，包括：由包含La和Hf的第一高电介质膜制成的栅极绝缘膜; 以及栅极，其由金属膜和多晶Si膜的叠层膜形成，并且形成在半导体衬底的主表面的有源区中并被由含氧的绝缘膜形成的元件分离部分包围 原子，第二高电介质膜，其含有Hf但其La含量小于第一高介电膜的La含量，形成在乘以元件分离部分的栅电极下面，而不是第一高介电膜。

公开(公告)号：US20170018556A1

公开(公告)日：2017-01-19

申请号：US15277996

申请日：2016-09-27

Applicant: Renesas Electronics Corporation

Inventor： Hiromasa YOSHIMORI ,  Hirofumi TOKITA

IPC: H01L27/115 ,  H01L29/06 ,  H01L23/535 ,  H01L29/36 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L27/1157 ,  H01L21/266 ,  H01L21/28282 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L23/535 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.

Abstract translation: 提供了具有改进的性能的半导体器件。 在半导体衬底上，通过第一绝缘膜形成虚拟控制栅电极。 在半导体衬底上，用于存储单元的存储栅电极经由具有内部电荷存储部分的第二绝缘膜形成，以便与虚拟控制栅电极相邻。 此时，存储栅电极的高度被调节为低于虚拟控制栅电极的高度。 然后，形成第三绝缘膜，以覆盖虚拟控制栅电极和存储栅电极。 然后，对第三绝缘膜进行抛光以露出虚拟控制栅电极。 此时，存储栅电极不露出。 然后，去除虚拟控制栅电极并用金属栅电极代替。

公开(公告)号：US20160315013A1

公开(公告)日：2016-10-27

申请号：US15091370

申请日：2016-04-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi TOKITA

IPC: H01L21/8234 ,  H01L29/45 ,  H01L29/167 ,  H01L21/265

CPC classification number: H01L21/823418 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823493 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/167 ,  H01L29/45 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7836

Abstract: Object is to provide a semiconductor device having improved reliability or performance.A high-breakdown-voltage n type transistor has source and drain regions having first, second, and third semiconductor regions, which are formed by ion implantation of a first impurity from the outside of a high-breakdown-voltage gate electrode, a second impurity from the outside of the high-breakdown-voltage gate electrode and a first sidewall insulating film, and a third impurity from the outside of the high-breakdown-voltage gate electrode and the first and second sidewall insulating films, respectively. The first and second impurities are implanted from a direction tilted by 45° relative to the main surface of the semiconductor substrate and the third impurity from a direction perpendicular thereto. The impurity concentration of the first semiconductor region is lower than that of the second one and the ion implantation energy of the first impurity is greater than that of the second impurity.

Abstract translation: 高耐压N型晶体管具有源极和漏极区，具有通过从高击穿电压栅电极的外部离子注入第一杂质而形成的第一，第二和第三半导体区，第二杂质 分别从高击穿电压栅电极的外侧和第一侧壁绝缘膜以及第三杂质从高击穿电压栅电极和第一和第二侧壁绝缘膜的外部开始。 第一和第二杂质从相对于半导体衬底的主表面倾斜45°的方向和与其垂直的方向从第三杂质注入。 第一半导体区域的杂质浓度低于第二半导体区域的杂质浓度，第一杂质的离子注入能量大于第二杂质的离子注入能量。