公开(公告)号：US20140354331A1

公开(公告)日：2014-12-04

申请号：US14461163

申请日：2014-08-15

Applicant: Renesas Electronics Corporation

Inventor： Kazuo SAKAMOTO ,  Naozumi MORINO ,  Kazuo TANAKA ,  Hiroyasu ISHIZUKA

IPC: H03K19/08 ,  H01L27/118

CPC classification number: H01L27/0288 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/11898 ,  H01L2027/11875 ,  H01L2224/05554 ,  H03K19/0175 ,  H03K19/08

Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Abstract translation: 半导体集成电路器件包括围绕核心区域布置的I / O单元。 每个I / O单元包括电平移位器电路，I / O逻辑电路和I / O缓冲电路。 布置I / O逻辑电路的I / O逻辑区域和布置I / O缓冲电路的I / O缓冲区域与布置有I / O单元的焊盘的区域重叠。 I / O逻辑区域和I / O缓冲区域在平行于核心区域的一侧的方向上并排布置。

公开(公告)号：US20180197850A1

公开(公告)日：2018-07-12

申请号：US15918659

申请日：2018-03-12

Applicant: Renesas Electronics Corporation

Inventor： Takeo TOBA ,  Kazuo TANAKA ,  Hiroyasu ISHIZUKA

IPC: H01L27/02 ,  H01L23/00 ,  H01L27/118

CPC classification number: H01L27/0292 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0251 ,  H01L27/11898 ,  H01L2224/05553 ,  H01L2224/06 ,  H01L2924/1301 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.

公开(公告)号：US20130264647A1

公开(公告)日：2013-10-10

申请号：US13910891

申请日：2013-06-05

Applicant: Renesas Electronics Corporation

Inventor： Takeo TOBA ,  Kazuo TANAKA ,  Hiroyasu ISHIZUKA

IPC: H01L27/02

CPC classification number: H01L27/0292 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0251 ,  H01L27/11898 ,  H01L2224/05553 ,  H01L2224/06 ,  H01L2924/1301 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.

Abstract translation: 一种具有“I / O单元上的PAD”结构的半导体集成电路器件，其中焊盘引线部分几乎位于I / O部分的中心，以便减小芯片布局面积。 在I / O部分中，晶体管最靠近半导体芯片的外围。 当在I / O部分的平面图中看到时，电阻位于晶体管的上方，并且第一和第二二极管位于电阻之上; 第二晶体管位于二极管之上; 并且逻辑块位于第二晶体管的上方，其间具有形成在金属布线层中的焊盘引线部分。 这允许通过第二晶体管的焊盘在相同的节点上，因此焊盘引线部分可以几乎位于I / O部分的中心。

公开(公告)号：US20130093508A1

公开(公告)日：2013-04-18

申请号：US13654415

申请日：2012-10-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuo SAKAMOTO ,  Naozumi MORINO ,  Kazuo TANAKA ,  Hiroyasu ISHIZUKA

IPC: H01L25/00

CPC classification number: H01L27/0288 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/11898 ,  H01L2027/11875 ,  H01L2224/05554 ,  H03K19/0175 ,  H03K19/08

Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Abstract translation: 半导体集成电路器件包括围绕核心区域布置的I / O单元。 每个I / O单元包括电平移位器电路，I / O逻辑电路和I / O缓冲电路。 布置I / O逻辑电路的I / O逻辑区域和布置I / O缓冲电路的I / O缓冲区域与布置有I / O单元的焊盘的区域重叠。 I / O逻辑区域和I / O缓冲区域在平行于核心区域的一侧的方向上并排布置。