公开(公告)号：US20140354331A1

公开(公告)日：2014-12-04

申请号：US14461163

申请日：2014-08-15

Applicant: Renesas Electronics Corporation

Inventor： Kazuo SAKAMOTO ,  Naozumi MORINO ,  Kazuo TANAKA ,  Hiroyasu ISHIZUKA

IPC: H03K19/08 ,  H01L27/118

CPC classification number: H01L27/0288 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/11898 ,  H01L2027/11875 ,  H01L2224/05554 ,  H03K19/0175 ,  H03K19/08

Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Abstract translation: 半导体集成电路器件包括围绕核心区域布置的I / O单元。 每个I / O单元包括电平移位器电路，I / O逻辑电路和I / O缓冲电路。 布置I / O逻辑电路的I / O逻辑区域和布置I / O缓冲电路的I / O缓冲区域与布置有I / O单元的焊盘的区域重叠。 I / O逻辑区域和I / O缓冲区域在平行于核心区域的一侧的方向上并排布置。

公开(公告)号：US20130341728A1

公开(公告)日：2013-12-26

申请号：US14011704

申请日：2013-08-27

Applicant: Renesas Electronics Corporation

Inventor： Takahiro HAYASHI ,  Shunsuke TOYOSHIMA ,  Kazuo SAKAMOTO ,  Naozumi MORINO ,  Kazuo TANAKA

IPC: H01L23/498

CPC classification number: H01L23/49844 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/05 ,  H01L24/06 ,  H01L24/49 ,  H01L27/0255 ,  H01L27/092 ,  H01L2224/02166 ,  H01L2224/05025 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/06102 ,  H01L2224/06133 ,  H01L2224/06143 ,  H01L2224/06153 ,  H01L2224/06163 ,  H01L2224/49105 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract translation: 本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。 在半导体衬底上形成输入/输出电路，接地布线和电源布线通过输入/输出电路，并且在其上形成用于焊盘的导电层。 输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成，电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。 连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出 到导电层。

公开(公告)号：US20170263550A1

公开(公告)日：2017-09-14

申请号：US15397762

申请日：2017-01-04

Applicant: Renesas Electronics Corporation

Inventor： Hiroki NISHIDA ,  Naozumi MORINO ,  Toshimi MIZUTANI

IPC: H01L23/528 ,  G06F17/50

CPC classification number: H01L23/528 ,  G06F17/5077 ,  H01L23/5226 ,  H01L28/00

Abstract: A metal wiring layer includes a plurality of hierarchical blocks each divided by a side that serves as a boundary. One of the hierarchical blocks is placed to extend along the outer periphery of the self hierarchical block, and includes: a shield ring wire formed by a single metal wire or by a plurality of metal wires; and a plurality of metal wires that are placed inside the shield ring wire and extend in a preferential direction determined in advance. The shield ring wire has a first section extending in the preferential direction and a second section extending in a non-preferential direction perpendicular to the preferential direction.

公开(公告)号：US20130093508A1

公开(公告)日：2013-04-18

申请号：US13654415

申请日：2012-10-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuo SAKAMOTO ,  Naozumi MORINO ,  Kazuo TANAKA ,  Hiroyasu ISHIZUKA

IPC: H01L25/00

CPC classification number: H01L27/0288 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/11898 ,  H01L2027/11875 ,  H01L2224/05554 ,  H03K19/0175 ,  H03K19/08

Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Abstract translation: 半导体集成电路器件包括围绕核心区域布置的I / O单元。 每个I / O单元包括电平移位器电路，I / O逻辑电路和I / O缓冲电路。 布置I / O逻辑电路的I / O逻辑区域和布置I / O缓冲电路的I / O缓冲区域与布置有I / O单元的焊盘的区域重叠。 I / O逻辑区域和I / O缓冲区域在平行于核心区域的一侧的方向上并排布置。