公开(公告)号：US20130341728A1

公开(公告)日：2013-12-26

申请号：US14011704

申请日：2013-08-27

Applicant: Renesas Electronics Corporation

Inventor： Takahiro HAYASHI ,  Shunsuke TOYOSHIMA ,  Kazuo SAKAMOTO ,  Naozumi MORINO ,  Kazuo TANAKA

IPC: H01L23/498

CPC classification number: H01L23/49844 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/05 ,  H01L24/06 ,  H01L24/49 ,  H01L27/0255 ,  H01L27/092 ,  H01L2224/02166 ,  H01L2224/05025 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/06102 ,  H01L2224/06133 ,  H01L2224/06143 ,  H01L2224/06153 ,  H01L2224/06163 ,  H01L2224/49105 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract translation: 本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。 在半导体衬底上形成输入/输出电路，接地布线和电源布线通过输入/输出电路，并且在其上形成用于焊盘的导电层。 输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成，电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。 连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出 到导电层。

公开(公告)号：US20130093508A1

公开(公告)日：2013-04-18

申请号：US13654415

申请日：2012-10-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuo SAKAMOTO ,  Naozumi MORINO ,  Kazuo TANAKA ,  Hiroyasu ISHIZUKA

IPC: H01L25/00

CPC classification number: H01L27/0288 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/11898 ,  H01L2027/11875 ,  H01L2224/05554 ,  H03K19/0175 ,  H03K19/08

Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Abstract translation: 半导体集成电路器件包括围绕核心区域布置的I / O单元。 每个I / O单元包括电平移位器电路，I / O逻辑电路和I / O缓冲电路。 布置I / O逻辑电路的I / O逻辑区域和布置I / O缓冲电路的I / O缓冲区域与布置有I / O单元的焊盘的区域重叠。 I / O逻辑区域和I / O缓冲区域在平行于核心区域的一侧的方向上并排布置。

公开(公告)号：US20140354331A1

公开(公告)日：2014-12-04

申请号：US14461163

申请日：2014-08-15

Applicant: Renesas Electronics Corporation

Inventor： Kazuo SAKAMOTO ,  Naozumi MORINO ,  Kazuo TANAKA ,  Hiroyasu ISHIZUKA

IPC: H03K19/08 ,  H01L27/118

CPC classification number: H01L27/0288 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/11898 ,  H01L2027/11875 ,  H01L2224/05554 ,  H03K19/0175 ,  H03K19/08

Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Abstract translation: 半导体集成电路器件包括围绕核心区域布置的I / O单元。 每个I / O单元包括电平移位器电路，I / O逻辑电路和I / O缓冲电路。 布置I / O逻辑电路的I / O逻辑区域和布置I / O缓冲电路的I / O缓冲区域与布置有I / O单元的焊盘的区域重叠。 I / O逻辑区域和I / O缓冲区域在平行于核心区域的一侧的方向上并排布置。

公开(公告)号：US20240021557A1

公开(公告)日：2024-01-18

申请号：US17864038

申请日：2022-07-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuo SAKAMOTO

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/17 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/81 ,  H01L21/563 ,  H01L2924/35121 ,  H01L2924/381 ,  H01L2224/81911 ,  H01L2224/83911 ,  H01L2224/17132 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/17133

Abstract: This invention provides a placement area with an enlarged bump pitch while avoiding the risk of underfill void generation in the bump process.
The number of bumps is not changed, but the bump pitch at the center is arranged in parallel with the drying direction of the flip-chip process in the drying direction, and an arrangement area in which n rows are enlarged by +b(μm) bump pitch is made, and the chip area is finely adjusted.
According to the invention, with respect to the dry air direction after flux cleaning, the power of the dry air does not change for creating a minute bump enlarged area parallel to the air in the central portion.

公开(公告)号：US20250046741A1

公开(公告)日：2025-02-06

申请号：US18775102

申请日：2024-07-17

Applicant: Renesas Electronics Corporation

Inventor： Keita TSUCHIYA ,  Shuuichi KARIYAZAKI ,  Kazuo SAKAMOTO

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/528

Abstract: The performance of a semiconductor device can be improved. A plurality of protruding electrodes of a semiconductor chip includes: a plurality of first protruding electrodes arranged at positions overlapping a first region of an insulating layer, a plurality of second protruding electrodes arranged at positions overlapping a second region of the insulating layer, and a plurality of third protruding electrodes arranged at positions overlapping a third region of the insulating layer. The plurality of first protruding electrodes is arranged at a first pitch, the plurality of second protruding electrodes is arranged at a second pitch, and the plurality of third protruding electrodes is arranged at a third pitch different from each of the first pitch and the second pitch.

公开(公告)号：US20190006364A1

公开(公告)日：2019-01-03

申请号：US15985280

申请日：2018-05-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuo SAKAMOTO ,  Toshiaki ITO

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/0259

Abstract: According to one embodiment, a semiconductor device includes a shallow P-well, a shallow N-well, a shallow P-well, and a shallow N-well formed in regions different from one another, a deep N-well formed in a part deeper than the shallow P-well and the shallow N-well, and a base material, and further includes a first transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, and a second transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, in which the shallow N-well is formed in such a way as to surround the peripheral edge of the region of the shallow P-well.