公开(公告)号：US20210272917A1

公开(公告)日：2021-09-02

申请号：US17148923

申请日：2021-01-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki SATO ,  Mitsunobu WANSAWA ,  Akira MATSUMOTO ,  Yoshinori DEGUCHI ,  Kentaro SAITO

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/56 ,  H01L21/48

Abstract: In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.

公开(公告)号：US20240120252A1

公开(公告)日：2024-04-11

申请号：US18358411

申请日：2023-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuhiro KINOSHITA ,  Mitsunobu WANSAWA

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29324 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/16598 ,  H01L2924/3512

Abstract: A semiconductor device according to one embodiment, includes: a wiring substrate having a core insulating layer; a semiconductor chip mounted on an upper surface of the wiring substrate; a plurality of solder balls formed on a lower surface of the wiring substrate; and a heat sink having a first portion fixed to a back surface of the semiconductor chip via a first adhesive layer, and a second portion located around the first portion and fixed to the wiring substrate via a second adhesive layer. Here, a portion of the plurality of solder balls is arranged at a position overlapping with each of the second portion of the heat sink and the second adhesive layer. Also, a second thickness of the second adhesive layer is greater than two times a first thickness of the first adhesive layer.