公开(公告)号：US20180040598A1

公开(公告)日：2018-02-08

申请号：US15730977

申请日：2017-10-12

Applicant: Renesas Electronics Corporation

Inventor： Bunji YASUMURA ,  Yoshinori DEGUCHI ,  Fumikazu TAKEI ,  Akio HASEBE ,  Naohiro MAKIHIRA ,  Mitsuyuki KUBO

IPC: H01L25/00 ,  H01L21/66 ,  H01L23/544 ,  H01L21/683 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L22/12 ,  H01L22/14 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2223/54493 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06131 ,  H01L2224/11009 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00

Abstract: To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

公开(公告)号：US20210272917A1

公开(公告)日：2021-09-02

申请号：US17148923

申请日：2021-01-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki SATO ,  Mitsunobu WANSAWA ,  Akira MATSUMOTO ,  Yoshinori DEGUCHI ,  Kentaro SAITO

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/56 ,  H01L21/48

Abstract: In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.

公开(公告)号：US20180374795A1

公开(公告)日：2018-12-27

申请号：US15774664

申请日：2016-02-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori DEGUCHI ,  Akinobu WATANABE

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/00 ,  H01L23/58 ,  H01L23/538 ,  H01L21/66

Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.

公开(公告)号：US20200328157A1

公开(公告)日：2020-10-15

申请号：US16911852

申请日：2020-06-25

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori DEGUCHI ,  Akinobu WATANABE

IPC: H01L23/535 ,  H01L21/3205 ,  H01L23/522 ,  H01L21/768 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00 ,  H01L23/58

Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.

公开(公告)号：US20200043877A1

公开(公告)日：2020-02-06

申请号：US16460552

申请日：2019-07-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kentaro SAITO ,  Takashi MORIYAMA ,  Yoshinori DEGUCHI

IPC: H01L23/00 ,  H01L23/522

Abstract: A semiconductor device includes semiconductor substrate having outer peripheral sides in plan view, and at least a pair of first bonding pad and second bonding pad formed over the semiconductor substrate. The second bonding pad has a shape obtained by rotating the first bonding pad by 180 degrees in plan view. The first bonding pad and the second bonding pad are arranged so as to face each other in a first direction crossing the outer peripheral side. The first bonding pad has a first portion and a second portion of rectangular shape in the second direction along the outer peripheral side. A width of the first portion in the first direction is greater than a width of the second portion in the first direction.

公开(公告)号：US20190295930A1

公开(公告)日：2019-09-26

申请号：US16281619

申请日：2019-02-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshinori DEGUCHI ,  Iwao NATORI ,  Seiya ISOZAKI

IPC: H01L23/495 ,  H01L23/532 ,  H01L23/00

Abstract: A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.

公开(公告)号：US20170005080A1

公开(公告)日：2017-01-05

申请号：US15268742

申请日：2016-09-19

Applicant: Renesas Electronics Corporation

Inventor： Bunji YASUMURA ,  Yoshinori DEGUCHI ,  Fumikazu TAKEI ,  Akio HASEBE ,  Naohiro MAKIHIRA ,  Mitsuyuki KUBO

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/544 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L22/12 ,  H01L22/14 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2223/54493 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06131 ,  H01L2224/11009 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00

Abstract: To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Abstract translation: 当存储器芯片安装在逻辑芯片上时，将形成在逻辑芯片的背面的识别标记的识别范围成像，识别范围的形状，逻辑芯片的多个凸点与 基于识别的结果执行上述存储芯片的多个投影电极，并且将上述存储芯片安装在逻辑芯片上。 此时，识别范围的形状与凸块的阵列形状的任何部分不同，结果，可以可靠地识别识别范围形状的识别标记，并且逻辑的凸块的对准 高精度地执行上述存储芯片的芯片和投影电极。