公开(公告)号：US20170053922A1

公开(公告)日：2017-02-23

申请号：US15236472

申请日：2016-08-14

Applicant: Renesas Electronics Corporation

Inventor： Kentaro SAITO ,  Hideki SUGIYAMA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792

CPC classification number: H01L21/28282 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/60 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

Abstract translation: 在半导体器件中，存储单元由彼此相邻的控制栅电极和存储栅电极形成，形成在控制栅电极下方的栅绝缘膜和形成在存储栅电极下方并具有电荷累积的绝缘膜 其中的部分。 此外，在该半导体器件中，电容元件由形成在上电极和下电极之间的下电极，上电极和电容绝缘膜形成。 下电极的厚度小于控制栅电极的厚度。

公开(公告)号：US20160035739A1

公开(公告)日：2016-02-04

申请号：US14884273

申请日：2015-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kentaro SAITO ,  Hiraku CHAKIHARA

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49 ,  H01L21/02 ,  H01L29/423 ,  H01L21/3213

CPC classification number: H01L27/11568 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/1157 ,  H01L29/0642 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: The performances of a semiconductor device are improved. The semiconductor device has a first control gate electrode and a second control gate electrode spaced along the gate length direction, a first cap insulation film formed over the first control gate electrode, and a second cap insulation film formed over the second control gate electrode. Further, the semiconductor device has a first memory gate electrode arranged on the side of the first control gate electrode opposite to the second control gate electrode, and a second memory gate electrode arranged on the side of the second control gate electrode opposite to the first control gate electrode. The end at the top surface of the first cap insulation film on the second control gate electrode side is situated closer to the first memory gate electrode side than the side surface of the first control gate electrode on the second control gate electrode side.

Abstract translation: 提高了半导体器件的性能。 半导体器件具有沿着栅极长度方向间隔开的第一控制栅电极和第二控制栅电极，形成在第一控制栅电极上的第一帽绝缘膜，以及形成在第二控制栅电极上的第二帽绝缘膜。 此外，半导体器件具有布置在与第二控制栅电极相对的第一控制栅极侧的第一存储栅极，以及布置在第二控制栅电极与第一控制栅相反的一侧的第二存储栅电极 栅电极。 第二控制栅电极侧的第一帽绝缘膜的顶面的端部比第二控制栅电极侧的第一控制栅电极的侧面更靠近第一存储栅电极侧。

公开(公告)号：US20210272917A1

公开(公告)日：2021-09-02

申请号：US17148923

申请日：2021-01-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki SATO ,  Mitsunobu WANSAWA ,  Akira MATSUMOTO ,  Yoshinori DEGUCHI ,  Kentaro SAITO

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/56 ,  H01L21/48

Abstract: In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.

公开(公告)号：US20160118394A1

公开(公告)日：2016-04-28

申请号：US14989999

申请日：2016-01-07

Applicant: Renesas Electronics Corporation

Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

IPC: H01L27/115 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

公开(公告)号：US20140242796A1

公开(公告)日：2014-08-28

申请号：US14079120

申请日：2013-11-13

Applicant: Renesas Electronics Corporation

Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

IPC: H01L21/3105 ,  H01L27/105 ,  H01L21/8234

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

公开(公告)号：US20160225902A1

公开(公告)日：2016-08-04

申请号：US15093048

申请日：2016-04-07

Applicant: Renesas Electronics Corporation

Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

IPC: H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

公开(公告)号：US20130149854A1

公开(公告)日：2013-06-13

申请号：US13662509

申请日：2012-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasushi ISHII ,  Hiraku CHAKIHARA ,  Kentaro SAITO

IPC: H01L21/82

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/82 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864

Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.

Abstract translation: 在包括在相同基板上具有不同特性的多个场效应晶体管的半导体器件的制造成品率方面的改进。 通过将各向异性干法蚀刻与各向同性湿蚀刻或各向同性干法蚀刻相结合，形成具有不同侧壁长度的三种类型的侧壁。 通过减少各向异性干蚀刻步骤的数量，在布置密度高的第三n型MISFET区域和第三p型MISFET区域中，可以防止半导体衬底在n型栅极之间被部分切割 彼此相邻的n型栅电极和彼此相邻的p型栅极之间，以及彼此相邻的p型栅电极。

公开(公告)号：US20200043877A1

公开(公告)日：2020-02-06

申请号：US16460552

申请日：2019-07-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kentaro SAITO ,  Takashi MORIYAMA ,  Yoshinori DEGUCHI

IPC: H01L23/00 ,  H01L23/522

Abstract: A semiconductor device includes semiconductor substrate having outer peripheral sides in plan view, and at least a pair of first bonding pad and second bonding pad formed over the semiconductor substrate. The second bonding pad has a shape obtained by rotating the first bonding pad by 180 degrees in plan view. The first bonding pad and the second bonding pad are arranged so as to face each other in a first direction crossing the outer peripheral side. The first bonding pad has a first portion and a second portion of rectangular shape in the second direction along the outer peripheral side. A width of the first portion in the first direction is greater than a width of the second portion in the first direction.

公开(公告)号：US20180053658A1

公开(公告)日：2018-02-22

申请号：US15796621

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Kentaro SAITO ,  Hideki SUGIYAMA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA

IPC: H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L21/28282 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/60 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

公开(公告)号：US20160172201A1

公开(公告)日：2016-06-16

申请号：US15050060

申请日：2016-02-22

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Hiraku CHAKIHARA

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/40 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/40117 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/66833

Abstract: The present invention improves the performance of a semiconductor device. In a manufacturing method of a semiconductor device, sacrificial oxide films are formed over the side surface of a control gate electrode formed in a memory cell region, the surface of a cap insulating film formed in the memory cell region, and the surface of the part, which remains in a peripheral circuit region, of an insulating film. The step of forming the sacrificial oxide films includes the steps of: oxidizing the side surface of the control gate electrode by a thermal oxidation method; and oxidizing the surface of the cap insulating film and the surface of the part, which remains in the peripheral circuit region, of the insulating film by an ISSG oxidation method.