公开(公告)号：US20190198462A1

公开(公告)日：2019-06-27

申请号：US16175522

申请日：2018-10-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuyuki NAKAGAWA ,  Keita TSUCHIYA ,  Yoshiaki SATO ,  Shuuichi KARIYAZAKI ,  Norio CHUJO ,  Masayoshi YAGYU ,  Yutaka UEMATSU

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/367 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.

公开(公告)号：US20180374788A1

公开(公告)日：2018-12-27

申请号：US16063280

申请日：2016-02-10

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki NAKAGAWA ,  Katsushi TERAJIMA ,  Keita TSUCHIYA ,  Yoshiaki SATO ,  Hiroyuki UCHIDA ,  Yuji KAYASHIMA ,  Shuuichi KARIYAZAKI ,  Shinji BABA

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member. In addition, the first terminal of the first semiconductor component is electrically connected to the wiring substrate via a first bump electrode without the first wiring member interposed therebetween.

公开(公告)号：US20180254252A1

公开(公告)日：2018-09-06

申请号：US15759211

申请日：2015-10-15

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki NAKAGAWA ,  Keita TSUCHIYA ,  Yoshiaki SATO ,  Shinji BABA

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/16 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L21/66

CPC classification number: H01L23/642 ,  G01R31/2836 ,  H01G2/06 ,  H01G4/38 ,  H01G4/40 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L22/12 ,  H01L23/12 ,  H01L23/16 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L25/00 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/46

Abstract: A semiconductor device includes a wiring substrate including a first surface and a second surface opposite to the first surface, a semiconductor chip including a plurality of chip electrodes and mounted over the wiring substrate, a first capacitor arranged at a position overlapping with the semiconductor chip in plan view and incorporated in the wiring substrate, and a second capacitor arranged between the first capacitor and a peripheral portion of the wiring substrate in plan view. Also, the second capacitor is inserted in series connection into a signal transmission path through which an electric signal is input to or output from the semiconductor chip.

公开(公告)号：US20170178985A1

公开(公告)日：2017-06-22

申请号：US15333693

申请日：2016-10-25

Applicant: Renesas Electronics Corporation

Inventor： Yoshiaki SATO ,  Yosuke KATSURA

IPC: H01L23/04 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L23/10

CPC classification number: H01L23/04 ,  H01L21/4817 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/73 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16196 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/3512

Abstract: A semiconductor device includes a semiconductor chip and a package structure mounted on a wiring substrate, and a lid for covering the semiconductor chip, which is fixed to the surface of the wiring substrate, without overlapping with the package structure in plan view. The lid includes an upper surface portion overlapping with the semiconductor chip, a flange portion fixed to the surface of the wiring substrate, and a slant portion for jointing the upper surface portion and the flange portion. Then, a distance from the surface of the wiring substrate to the top surface of the upper surface portion is larger than a distance from the surface of the wiring substrate to the top surface of the flange portion.

公开(公告)号：US20210272917A1

公开(公告)日：2021-09-02

申请号：US17148923

申请日：2021-01-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki SATO ,  Mitsunobu WANSAWA ,  Akira MATSUMOTO ,  Yoshinori DEGUCHI ,  Kentaro SAITO

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/56 ,  H01L21/48

Abstract: In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.

公开(公告)号：US20200098679A1

公开(公告)日：2020-03-26

申请号：US16547294

申请日：2019-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki SATO ,  Yoshinori MIYAKI ,  Junichi ARITA

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.