公开(公告)号：US20210066445A1

公开(公告)日：2021-03-04

申请号：US16889725

申请日：2020-06-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuhiko IWAKIRI ,  Akira MATSUMOTO

IPC: H01L49/02 ,  H01L21/67 ,  H01L21/768

Abstract: A semiconductor device including a multilayer wiring layer comprising a first wiring, a first insulating film formed on the multilayer wiring layer and having a first opening exposing a portion of the first wiring, a second insulating film formed on the first insulating film and having a second opening continuing with the first opening, and an inductor formed of the first wiring, and a second wiring electrically connected with the first wiring through a via formed in the first opening. A side surface of the via contacts with the first insulating film, and does not contact with the second insulating film.

公开(公告)号：US20190206789A1

公开(公告)日：2019-07-04

申请号：US16192521

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro KUWAJIMA ,  Yasutaka NAKASHIBA ,  Akira MATSUMOTO ,  Akio ONO ,  Tetsuya IIDA

IPC: H01L23/522 ,  H01L49/02 ,  H01L29/93 ,  H01L27/06 ,  H03L7/099

CPC classification number: H01L23/5223 ,  H01L27/0629 ,  H01L28/86 ,  H01L29/93 ,  H03L7/099

Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the cod is 7 μm or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 μm or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view. Even if such wirings (linear wiring parts) are arranged under the coil, the characteristics (for example, RF characteristics) of the semiconductor device are not deteriorated. In addition, the area of the semiconductor device can be reduced or high integration of elements can be realized by laminating elements (for example, MOM capacitance elements and the like) having the coil and the linear wiring parts.

公开(公告)号：US20180294222A1

公开(公告)日：2018-10-11

申请号：US16009429

申请日：2018-06-15

Applicant: Renesas Electronics Corporation

Inventor： Teruhiro KUWAJIMA ,  Akira MATSUMOTO ,  Yasutaka NAKASHIBA ,  Takashi IWADARE

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L23/4952 ,  H01L23/49551 ,  H01L2224/05554 ,  H01L2224/4813 ,  H01L2224/49175

Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.

公开(公告)号：US20170077013A1

公开(公告)日：2017-03-16

申请号：US15341332

申请日：2016-11-02

Applicant: Renesas Electronics Corporation

Inventor： Akira MATSUMOTO ,  Yoshinao MIURA ,  Yasutaka NAKASHIBA

IPC: H01L23/495 ,  H01L23/00 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L23/49562 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/4805 ,  H01L2224/4813 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

Abstract translation: 公开了一种半导体器件，其中由布线产生的电阻分量减小。 多个晶体管单元沿第一方向并排布置，每个晶体管单元具有多个晶体管。 晶体管的栅电极沿第一方向延伸。 第一源极布线在第一晶体管单元和第二晶体管单元之间延伸，并且第一漏极布线在第二晶体管单元和第三晶体管单元之间延伸。 第二漏极布线在第一晶体管单元的与第一源极布线延伸的一侧相反的一侧延伸，并且第二源极布线在与第二漏极布线延伸的一侧相反的一侧延伸。

公开(公告)号：US20170062332A1

公开(公告)日：2017-03-02

申请号：US15186734

申请日：2016-06-20

Applicant: Renesas Electronics Corporation

Inventor： Teruhiro KUWAJIMA ,  Akira MATSUMOTO ,  Yasutaka NAKASHIBA ,  Takashi IWADARE

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L23/4952 ,  H01L23/49551 ,  H01L2224/05554 ,  H01L2224/4813 ,  H01L2224/49175

Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.

Abstract translation: SOP具有半导体芯片。 芯片包括一对下层线圈和层叠在其间形成的层间绝缘膜的上层线圈，电耦合到上层线圈的第一电路单元和多个电极焊盘。 此外，它具有用于电耦合上层线圈和第一电路单元的导线，布置在半导体芯片周围的多个内部引线和外部引线，用于电连接半导体芯片的电极焊盘和内部 引线和用于覆盖半导体芯片的树脂制密封构件。 电线沿电线的延伸方向延伸。

公开(公告)号：US20220020604A1

公开(公告)日：2022-01-20

申请号：US16930106

申请日：2020-07-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki TSUCHIYA ,  Akira MATSUMOTO

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a package substrate, a semiconductor chip and a solder bump. The semiconductor chip is disposed on the package substrate. The package substrate includes a first electrode pad, and a first insulating film formed such that the first insulating film exposes a first portion of a surface of the first electrode pad. The semiconductor chip includes a second electrode pad and a second insulating film formed such that the second insulating film exposes a second portion of a surface of the second electrode pad. The second electrode pad is formed on the first electrode pad through the solder bump. L2/L1 is 0.63 or more in a cross section passing through the first electrode pad, the solder bump and the second electrode pad. A first length of the first portion and a second length of the second portion are defined as L1 and L2, respectively.

公开(公告)号：US20210272917A1

公开(公告)日：2021-09-02

申请号：US17148923

申请日：2021-01-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki SATO ,  Mitsunobu WANSAWA ,  Akira MATSUMOTO ,  Yoshinori DEGUCHI ,  Kentaro SAITO

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/56 ,  H01L21/48

Abstract: In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.

公开(公告)号：US20150263002A1

公开(公告)日：2015-09-17

申请号：US14727446

申请日：2015-06-01

Applicant: Renesas Electronics Corporation

Inventor： Akira MATSUMOTO ,  Yoshinao MIURA ,  Yasutaka NAKASHIBA

IPC: H01L27/088 ,  H01L23/492 ,  H01L27/06 ,  H01L23/528 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49562 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/4805 ,  H01L2224/4813 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

Abstract translation: 公开了一种半导体器件，其中由布线产生的电阻分量减小。 多个晶体管单元沿着第一方向（视图中的Y方向）并排布置，每个晶体管单元具有多个晶体管。 晶体管的栅电极沿第一方向延伸。 第一源极布线在第一晶体管单元和第二晶体管单元之间延伸，并且第一漏极布线在第二晶体管单元和第三晶体管单元之间延伸。 第二漏极布线在第一晶体管单元的与第一源极布线延伸的一侧相反的一侧延伸，并且第二源极布线在与第二漏极布线延伸的一侧相反的一侧延伸。