公开(公告)号：US11211406B2

公开(公告)日：2021-12-28

申请号：US15251238

申请日：2016-08-30

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Ryuta Tsuchiya ,  Toshiaki Iwamatsu

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L27/11 ,  H03K17/687 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/105

摘要： To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

公开(公告)号：US09515170B2

公开(公告)日：2016-12-06

申请号：US15017459

申请日：2016-02-05

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Toshiaki Iwamatsu ,  Takashi Terada ,  Hirofumi Shinohara ,  Kozo Ishikawa ,  Ryuta Tsuchiya ,  Kiyoshi Hayashi

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L21/308 ,  H01L21/321 ,  H01L21/265

CPC分类号： H01L29/66795 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/321 ,  H01L29/785

摘要： An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

摘要翻译： 本发明的目的是提供一种半导体器件，其具有通过以高精度形成鳍状半导体部分和栅极电极或通过改善元件之间的特性变化而具有优异的特性的鳍型晶体管。 本发明是一种半导体器件，包括：鳍状半导体部分，其一侧形成有源极区域，在其另一侧形成有漏极区域，以及形成在源极区域和漏极区域之间的栅电极， 翅片状半导体部分，其间具有栅极绝缘膜。 解决根据本发明的问题的一种解决方案是栅电极使用可湿蚀刻的金属材料或硅化物材料。

公开(公告)号：US11695014B2

公开(公告)日：2023-07-04

申请号：US17528585

申请日：2021-11-17

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Ryuta Tsuchiya ,  Toshiaki Iwamatsu

IPC分类号： H01L27/12 ,  H01L21/84 ,  H10B10/00 ,  H03K17/687 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/105

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/0649 ,  H03K17/6872 ,  H10B10/00 ,  H10B10/12 ,  H10B10/18 ,  H01L21/823878 ,  H01L27/105

摘要： To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at most 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.