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    Semiconductor device and method of manufacturing the same
    2.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09166041B2

    公开(公告)日：2015-10-20

    申请号：US14459999

    申请日：2014-08-14

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hirofumi Shinohara ,  Hidekazu Oda ,  Toshiaki Iwamatsu

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

    CPC classification number: H01L27/1203 ,  H01L21/26586 ,  H01L21/76229 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/36 ,  H01L29/45 ,  H01L29/66598 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7835

    Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

    Abstract translation: 在具有通过绝缘层形成在半导体衬底上的半导体层的SOI衬底中，在nMIS形成区域和pMIS形成区域中的每个半导体层中形成MISFET。 在供电区域中，去除半导体层和绝缘层。 在半导体基板中，形成p型半导体区域，以便包括nMIS形成区域和一个供电区域，并且形成n型半导体区域以便包括pMIS形成区域，而另一个 的供电区域。 在半导体衬底中，形成具有比p型半导体区域低的杂质浓度的p型阱，以便容纳p型半导体区域，并且具有比n型半导体的杂质浓度低的n型阱 区域形成为包含n型半导体区域。

    Semiconductor device and method for manufacturing the same
    5.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09515170B2

    公开(公告)日：2016-12-06

    申请号：US15017459

    申请日：2016-02-05

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Toshiaki Iwamatsu ,  Takashi Terada ,  Hirofumi Shinohara ,  Kozo Ishikawa ,  Ryuta Tsuchiya ,  Kiyoshi Hayashi

    IPC: H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L21/308 ,  H01L21/321 ,  H01L21/265

    CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/321 ,  H01L29/785

    Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

    Abstract translation: 本发明的目的是提供一种半导体器件，其具有通过以高精度形成鳍状半导体部分和栅极电极或通过改善元件之间的特性变化而具有优异的特性的鳍型晶体管。 本发明是一种半导体器件，包括：鳍状半导体部分，其一侧形成有源极区域，在其另一侧形成有漏极区域，以及形成在源极区域和漏极区域之间的栅电极， 翅片状半导体部分，其间具有栅极绝缘膜。 解决根据本发明的问题的一种解决方案是栅电极使用可湿蚀刻的金属材料或硅化物材料。

    Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage
    6.
    发明授权
    Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage 有权
    半导体存储器件即使在低电源电压下也能够稳定地执行写入和读取而不增加电流消耗

    公开(公告)号：US09218873B2

    公开(公告)日：2015-12-22

    申请号：US14151581

    申请日：2014-01-09

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Koji Nii ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

    IPC: G11C5/14 ,  G11C11/412 ,  G11C5/06 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

    Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    7.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
    半导体器件的制造方法

    公开(公告)号：US20140179076A1

    公开(公告)日：2014-06-26

    申请号：US14133605

    申请日：2013-12-18

    Applicant: Renesas Electronics Corporation

    Inventor： Hirofumi Shinohara

    IPC: H01L27/105

    CPC classification number: H01L21/28273 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

    Abstract: Even when a semiconductor device having field effect transistors driven by relatively different power supply voltages provided over a semiconductor substrate is manufactured by the gate-last process, the breakdown voltage of the transistor on the higher voltage side can be ensured.When forming, over the substrate by the gate-last process, a MOSFET of a core region driven by a first power supply voltage and a MOSFET of a high-voltage region driven by a second power supply voltage higher than the first power supply voltage, the thickness of the hard mask film formed over a dummy gate film of the high-voltage region is made thicker than that of the hard mask film formed over a dummy gate film of the core region, prior to a process of patterning a dummy gate of the MOSFET of the core region and the MOSFET of the high-voltage region. Thereby, the breakdown voltage of MOSFET of the high-voltage region can be ensured.

    Abstract translation: 即使通过栅极最后工艺制造具有由半导体衬底上的相对不同的电源电压驱动的场效应晶体管的半导体器件，也可以确保高电压侧的晶体管的击穿电压。 当通过栅极最后工艺在衬底上形成由第一电源电压驱动的芯区域的MOSFET和由比第一电源电压高的第二电源电压驱动的高电压区域的MOSFET时， 在高电压区域的伪栅极膜之上形成的硬掩模膜的厚度比在芯区域的伪栅极膜上形成的硬掩模膜的厚度厚， 芯区的MOSFET和高压区的MOSFET。 由此，能够确保高电压区域的MOSFET的击穿电压。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130175611A1

    公开(公告)日：2013-07-11

    申请号：US13735857

    申请日：2013-01-07

    Applicant: Renesas Electronics Corporation

    Inventor： Hirofumi Shinohara ,  Hiromasa Yoshimori ,  Toshiaki Iwamatsu ,  Hidekazu Oda

    IPC: H01L21/02 ,  H01L27/088

    CPC classification number: H01L21/02697 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/0924

    Abstract: An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.

    Abstract translation: 降低了形成低电压场效应晶体管的区域的顶视图中的区域，并且降低了形成高电压场效应晶体管的区域的顶视图中的区域。 形成低电压场效应晶体管（第一nMIS和第一pMIS）的有源区域由从元件隔离部分的表面突出的半导体衬底的第一凸部和高电场电场效应晶体管的有源区域构成， 形成电压场效应晶体管（第二nMIS和第二pMIS）由半导体衬底的从元件隔离部分的表面突出的第二凸部和形成在半导体衬底中的沟槽部分构成。

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