公开(公告)号：US20130207158A1

公开(公告)日：2013-08-15

申请号：US13764479

申请日：2013-02-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Daisuke ARAI ,  Sakae KUBO ,  Yuta IKEGAMI

IPC: H01L29/739

CPC classification number: H01L29/7393 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/66333 ,  H01L29/7395

Abstract: To improve a manufacture yield of semiconductor devices each including an IGBT, an active region defined by an insulating film and where an element of an IGBT is formed has a first long side and a second long side spaced at a predetermined distance apart from each other and extended in a first direction in a planar view. One end of the first long side has a first short side forming a first angle with the first long side, and one end of the second long side has a second short side forming a second angle with the second long side. The other end of the first long side has a third short side forming a third angle with the first long side, and the other end of the second long side has a fourth short side forming a fourth angle with the second long side. The first angle, the second angle, the third angle, and the fourth angle are in a range larger than 90 degrees and smaller than 180 degrees.

Abstract translation: 为了提高包括IGBT的半导体器件的制造成品率，由绝缘膜限定的有源区域和形成有IGBT的元件的第一长边和第二长边彼此隔开预定距离， 在平面视图中沿第一方向延伸。 第一长边的一端具有与第一长边形成第一角度的第一短边，第二长边的一端具有与第二长边形成第二角度的第二短边。 第一长边的另一端具有与第一长边形成第三角度的第三短边，而第二长边的另一端具有与第二长边形成第四角度的第四短边。 第一角度，第二角度，第三角度和第四角度在大于90度且小于180度的范围内。

公开(公告)号：US20150011081A1

公开(公告)日：2015-01-08

申请号：US14492382

申请日：2014-09-22

Applicant: RENESAS ELECTRONICS CORPORATION ,  HITACHI ULSI SYSTEMS CO., LTD.

Inventor： Sumito NUMAZAWA ,  Yoshito NAKAZAWA ,  Masayoshi KOBAYASHI ,  Satoshi KUDO ,  Yasuo IMAI ,  Sakae KUBO ,  Takashi SHIGEMATSU ,  Akihiro OHNISHI ,  Kozo UESAWA ,  Kentaro OISHI

IPC: H01L21/28

CPC classification number: H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract translation: 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的方向的深度方向上的第一导电类型的半导体层的主表面形成沟槽， 在沟槽的内表面上形成包括热氧化膜和沉积膜的栅极绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成 用作沟道形成区域的第二导电类型的半导体区域，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US20140225189A1

公开(公告)日：2014-08-14

申请号：US14259702

申请日：2014-04-23

Applicant: RENESAS ELECTRONICS CORPORATION ,  HITACHI ULSI SYSTEMS CO., LTD.

Inventor： Sumito NUMAZAWA ,  Yoshito NAKAZAWA ,  Masayoshi KOBAYASHI ,  Satoshi KUDO ,  Yasuo IMAI ,  Sakae KUBO ,  Takashi SHIGEMATSU ,  Akihiro OHNISHI ,  Kozo UESAWA ,  Kentaro OISHI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract translation: 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的方向的深度方向上的第一导电类型的半导体层的主表面形成沟槽， 在沟槽的内表面上形成包括热氧化膜和沉积膜的栅极绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成 用作沟道形成区域的第二导电类型的半导体区域，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。