公开(公告)号：US20170359097A1

公开(公告)日：2017-12-14

申请号：US15617738

申请日：2017-06-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi UCHIDA ,  Takafumi KURAMOTO

IPC: H04B1/44 ,  H01L23/522 ,  H04B5/00 ,  H01L23/58 ,  H01L49/02 ,  H01L23/528 ,  H03F3/213 ,  H01L23/552 ,  H01L27/06 ,  H03B5/12 ,  H03F3/195

CPC classification number: H04B1/44 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/552 ,  H01L23/585 ,  H01L27/0617 ,  H01L27/0629 ,  H01L28/10 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B2200/004 ,  H03B2200/0072 ,  H03B2201/025 ,  H03F1/565 ,  H03F3/195 ,  H03F3/213 ,  H03F3/245 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45731 ,  H04B5/0081

Abstract: A semiconductor device and a communication circuit capable of reducing the effect of a noise generated in an inductor are provided. A semiconductor device according to an embodiment includes a substrate, a first circuit disposed in a first area of the substrate, a second circuit disposed in a second area of the substrate, the second circuit being configured to operate selectively with the first circuit, a first inductor disposed in the second area and connected to the first circuit, and a second inductor disposed in the first area and connected to the second circuit.

公开(公告)号：US20170345755A1

公开(公告)日：2017-11-30

申请号：US15479978

申请日：2017-04-05

Applicant: Renesas Electronics Corporation

Inventor： Shinichi UCHIDA ,  Keiichiro TANAKA ,  Takafumi KURAMOTO

IPC: H01L23/522 ,  H01L23/552 ,  H01L23/532 ,  H01L23/528 ,  G01R19/00 ,  G01R15/18 ,  H01L21/3205 ,  H01F41/04 ,  H01F27/34 ,  H01F27/28 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L23/5227 ,  G01R15/18 ,  G01R15/181 ,  G01R19/0092 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/34 ,  H01F41/041 ,  H01F2017/0073 ,  H01F2017/008 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/76224 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53271 ,  H01L23/552 ,  H01L29/0649

Abstract: According to one embodiment, a semiconductor device 1 includes an Si substrate 11, an inductor 12 formed in wiring layers disposed above the Si substrate 11, and a shield 13 formed so as to surround the inductor 12, in which the shield 13 includes metals 105 to 109 formed in, among the wiring layers, a layer in which the inductor 12 is formed and a layer above that layer, and a silicide 104 formed between the Si substrate 11 and the wiring layers above the Si substrate 11.

公开(公告)号：US20180182751A1

公开(公告)日：2018-06-28

申请号：US15796816

申请日：2017-10-29

Applicant: Renesas Electronics Corporation

Inventor： Shinichi UCHIDA ,  Takafumi KURAMOTO ,  Yasutaka NAKASHIBA

IPC: H01L27/06 ,  H01L27/12 ,  H01L29/93 ,  H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66174 ,  H01L29/93 ,  H01L29/94

Abstract: A semiconductor device of the present invention includes, in a region 1C, a top electrode made by a semiconductor layer of an SOI substrate, a capacitive insulating film made by an insulating layer, a bottom electrode made by a supporting board, and a lead part (a high-concentration impurity region of an n type) of the bottom electrode coupled to the supporting board. An SOI transistor in a region 1B is formed over a main surface of the semiconductor layer over the insulating layer as a thin film, and threshold voltage can be adjusted by applying a voltage to a well arranged on the rear face side of the insulating layer.