公开(公告)号：US20230103256A1

公开(公告)日：2023-03-30

申请号：US17892626

申请日：2022-08-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya USAMI ,  Yoshiki MARUYAMA ,  Yuki MURAYAMA ,  Yuji ISHII

IPC: H01L23/00

Abstract: A semiconductor device includes: a semiconductor substrate having first and second main surfaces; interlayer insulating films laminated on the first main surface in a thickness direction from the second main surface toward the first main surface; a top wiring arranged on a top interlayer insulating film of the plurality of interlayer insulating films, which is provided farthest from the first main surface in the thickness direction; and a passivation film arranged on the top interlayer insulating film so as to cover the top wiring. The top wiring includes a first wiring portion and a second wiring portion that extend in a first direction in plan view and are adjacent to each other in a second direction orthogonal to the first direction. A first distance between an upper surface of the top wiring and the top interlayer insulating film in the thickness direction is 2.7 μm or more.

公开(公告)号：US20190326434A1

公开(公告)日：2019-10-24

申请号：US16375634

申请日：2019-04-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroaki SEKIKAWA ,  Takahiro MORI ,  Yuji ISHII

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L21/033 ,  H01L21/308 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device of one embodiment includes the steps of: forming a drift region in a first surface of a semiconductor substrate; forming a body region having a first portion disposed in the first surface, and a second portion disposed in the first surface so as to surround the first portion and the drift region; forming a hard mask, having an opening over the drift region, in the first surface; forming a reverse conductivity region in the first surface by ion implantation using the hard mask; forming a trench in the first surface by anisotropic etching using the hard mask; and embedding an isolation film in the trench. The ion implantation is performed obliquely to the first surface such that ions are implanted below a first edge part, which is located on a first portion side of the opening, of the hard mask.

公开(公告)号：US20190259749A1

公开(公告)日：2019-08-22

申请号：US16248251

申请日：2019-01-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuji ISHII

IPC: H01L27/07 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/40

Abstract: Provided are a semiconductor device capable of preventing erroneous operation and providing a field plate effect, and a method of manufacturing the semiconductor device. In a diode, a gate electrode, a p+ source region, and an n-type body region are electrically coupled to one another. A contact region is disposed between the n-type body region and the p+ source region in a first surface of a semiconductor substrate.

公开(公告)号：US20200273990A1

公开(公告)日：2020-08-27

申请号：US16783617

申请日：2020-02-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuji ISHII

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/761 ,  H01L21/762 ,  H01L27/092 ,  H01L29/36

Abstract: The n-type body extension region BER is separated from the n+ buried region BL by the p-type impurity region PIR and is in contact with the p-type drift region DFT1. At the end of the n-type body extension region BER closest to the p+ drain region DC, the first portion FP of the n-type body extension region BER located closest to the second surface SS is located closer to the p+ drain region DC than the second portion SP of the n-type body extension region BER located at the first surface FS, and is located closer to the second surface SS than the bottom surface BS of the element isolation insulating film SIS.