公开(公告)号：US20240120406A1

公开(公告)日：2024-04-11

申请号：US18449763

申请日：2023-08-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI ,  Yoshiki MARUYAMA

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28

CPC classification number: H01L29/66348 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28211

Abstract: It is related to improving a performance of a semiconductor device and suppressing yield deterioration. Using a resist pattern as a mask, an ion-implantation is performed from an upper surface of a semiconductor substrate to form an ion-implanted layer in the semiconductor substrate. By subsequently, another ion-implantation is performed. Then, another ion-implanted layer is formed in the semiconductor substrate so as to overlap with the ion-implanted layer. Next, a heat treatment is performed on the semiconductor substrate to diffuse impurities contained in the ion-implanted layers, thereby an p-type floating region is formed.

公开(公告)号：US20230103256A1

公开(公告)日：2023-03-30

申请号：US17892626

申请日：2022-08-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya USAMI ,  Yoshiki MARUYAMA ,  Yuki MURAYAMA ,  Yuji ISHII

IPC: H01L23/00

Abstract: A semiconductor device includes: a semiconductor substrate having first and second main surfaces; interlayer insulating films laminated on the first main surface in a thickness direction from the second main surface toward the first main surface; a top wiring arranged on a top interlayer insulating film of the plurality of interlayer insulating films, which is provided farthest from the first main surface in the thickness direction; and a passivation film arranged on the top interlayer insulating film so as to cover the top wiring. The top wiring includes a first wiring portion and a second wiring portion that extend in a first direction in plan view and are adjacent to each other in a second direction orthogonal to the first direction. A first distance between an upper surface of the top wiring and the top interlayer insulating film in the thickness direction is 2.7 μm or more.

公开(公告)号：US20140312406A1

公开(公告)日：2014-10-23

申请号：US14173074

申请日：2014-02-05

Applicant: Renesas Electronics Corporation

Inventor： Masao INOUE ,  Yoshiki MARUYAMA ,  Akio NISHIDA ,  Yorinobu KUNIMUNE ,  Kota FUNAYAMA

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/4925 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/28035 ,  H01L21/28176 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66825

Abstract: To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23).

Abstract translation: 为了控制层叠多晶硅膜上的晶粒生长，提供了制造半导体器件的方法。 该方法包括：在衬底（10）上形成第一多晶硅膜（21）; 在所述第一多晶硅膜（21）的表面上形成层间氧化物层（22）; 形成与第一多晶硅膜（21）上方的层间氧化物层（22）接触的第二多晶硅膜（23）。 在形成第二多晶硅膜（23）之后，在含氮气体气氛中，在高于第一和第二多晶硅膜的成膜温度的温度下进行退火。